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XC2C64A

Features: • Optimized for 1.8V systems - Industry's fastest low power CPLD - Densities from 32 to 512 macrocells• Industry's best 0.18 micron CMOS CPLD - Optimized architecture for effective logic synthesis - Multi-voltage I/O operation - 1.5V to 3.3V• Advanced system features - ...

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XC2C64A: Features: • Optimized for 1.8V systems - Industry's fastest low power CPLD - Densities from 32 to 512 macrocells• Industry's best 0.18 micron CMOS CPLD - Optimized architecture for effec...

XC2C64A Data Sheet

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Part Number:
XC2C64A
Supply Ability:
5000

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  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/12/21

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Product Details

Description



Features:

• Optimized for 1.8V systems
  - Industry's fastest low power CPLD
  - Densities from 32 to 512 macrocells
• Industry's best 0.18 micron CMOS CPLD
  - Optimized architecture for effective logic synthesis
  - Multi-voltage I/O operation - 1.5V to 3.3V
• Advanced system features
  - Fastest in system programming
` 1.8V ISP using IEEE 1532 (JTAG) interface
  - On-The-Fly Reconfiguration (OTF)
  - IEEE1149.1 JTAG Boundary Scan Test
  - Optional Schmitt trigger input (per pin)
  - Multiple I/O banks on all devices
  - Unsurpassed low power management
` DataGATE external signal control
  - Flexible clocking modes
` Optional DualEDGE triggered registers
` Clock divider (÷ 2,4,6,8,10,12,14,16)
` CoolCLOCK
  - Global signal options with macrocell control
` Multiple global clocks with phase selection per macrocell
` Multiple global output enables
` Global set/reset
  - Abundant product term clocks, output enables and set/resets
  - Efficient control term clocks, output enables and set/resets for each macrocell and shared across function blocks
  - Advanced design security
  - Open-drain output option for Wired-OR and LED drive
  - Optional bus-hold, 3-state or weak pullup on select I/O pins
  - Optional configurable grounds on unused I/Os
  - Mixed I/O voltages compatible with 1.5V, 1.8V, 2.5V, and 3.3V logic levels on all parts
  - SSTL2_1,SSTL3_1, and HSTL_1 on 128 macrocell and denser devices
  - Hot pluggable
• PLA architecture
  - Superior pinout retention
  - 100% product term routability across function block
• Wide package availability including fine pitch:
  - Chip Scale Package (CSP) BGA, Fine Line BGA, TQFP, PQFP, VQFP, PLCC, and QFN packages
  - Pb-free available for all packages
• Design entry/verification using Xilinx and industry standard CAE tools
• Free software support for all densities using Xilinx WebPACK™
• Industry leading nonvolatile 0.18 micron CMOS process
  - Guaranteed 1,000 program/erase cycles
  - Guaranteed 20 year data retention


Specifications

Symbol Parameter Min. Max. Unit
VCC(2) Supply voltage relative to GND 0.5 2.0 V
VI(3) Input voltage relative to GND 0.5 4.0 V
TJ Maximum junction temperature 40 150 °C
TSTR Storage temperature 65 150 °C
Notes:
1. Stresses above those listed may cause malfunction or permanent damage to the device. This is a stress rating only. Functional operation at these or any other condition above those indicated in the operational and programming specification is not implied.
2. The chip supply voltage should rise monotonically.
3. Maximum DC undershoot below GND must be limited to either 0.5V or 10 mA, whichever is easier to achieve. During transitions, the device pins may undershoot to 2.0V or overshoot to 4.5 V, provided this over- or undershoot lasts less than 10 ns and with the forcing current being limited to 200 mA. The I/O voltage may never exceed 4.0V.
4. For soldering guidelines and thermal considerations, see the Device Packaging information on the Xilinx website. For Pb-free packages, see XAPP427.


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