XC2C64

Notes:
1. Maximum DC undershoot below GND must be limited to either 0.5V or 10 mA, whichever is easiest to achieve. During transitions, the device pins may undershoot to 2.0v or overshoot to +3.9V, provided this over or undershoot lasts less than 10 ns and with the forcing current being limited to 200 mA.

The CoolRunner-II 64-macrocell XC2C64 is designed for both high performance and low power applications. This lends power savings to high-end communication equipment and speed to battery operated devices.

This XC2C64 consists of four Function Blocks inter-connected by a low power Advanced Interconnect Matrix (AIM).

The AIM feeds 40 inputs to each Function Block. The Function Blocks consist of a 40 by 56 p-term PLA and 16 macrocells which contain numerous configuration bits that allow for combinational or registered modes of operation. Additionally, these registers can be globally reset or preset and configured as a D or T flip-flop or as a D latch. There are also multiple clock signals, both global and local product term based, on a per macrocell basis. Output control signals include slew rate control, bus hold and open drain. An additional Schmitt-trigger input is available on a per input pin basis.

In addition to combinatorial and registered outputs, the registers may be configured as fast inputs.

Clocking is available on a global or Function Block basis. Three global clocks are available for all Function Blocks as a synchronous clock source. Global clocks are additionally used to set or preset individual macrocell registers on power up. Local clocks are generated in specific Function Blocks and only available to macrocell registers in that Function Block.

A DualEDGE flip-flop feature is also available on a per macrocell basis. This feature allows performance where it is needed without raising the total power consumption of the entire device.

The CoolRunner-II 64-macrocell CPLD is I/O compatible with standard LVTTL33 and LVCMOS18, 25, and 33 volts (see Table 1).