Features: • Simplifies Backplane Communications• Monitor Fault and Hot Docking Conditions• Ten Level Selectable Input Threshold• Two Fully Redundant SPI Serial I/O Ports• Programmable Output or Input Port Pins -16 General I/O pins -8 bit Port with 4 Handshake Modes&...
X5114: Features: • Simplifies Backplane Communications• Monitor Fault and Hot Docking Conditions• Ten Level Selectable Input Threshold• Two Fully Redundant SPI Serial I/O Ports...
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• Simplifies Backplane Communications
• Monitor Fault and "Hot Docking" Conditions
• Ten Level Selectable Input Threshold
• Two Fully Redundant SPI Serial I/O Ports
• Programmable Output or Input Port Pins
-16 General I/O pins
-8 bit Port with 4 Handshake Modes
• Single Read Input Mode
• Multiple Read Input Mode
• Output Mode
• Bidirectional Mode
-Port Tristate Control
• Programmable Interrupt and Mask Options
• 8-bit Direct Address Decoder allows Cascaded
255+ devices on one SPI bus
• 4K bits of EEPROM with 32 byte page write
• Default Output Data on Port at Power-up
• High Reliability EEPROM
-Endurance - 105 Data Changes
-Data Retention - 100 years
• 44-Pin PLCC, 48-Lead TQFP
Temperature Under Bias .........................-65 to +135
Storage Temperature...............................-65 to +150
Voltage on any pin with respect to Vss............-1V to +7V
DC Output Current.................................................. 10mA
Lead Temperature (Soldering, 10 Seconds) .............300
The X5114 is a single-chip system controller that is used in applications such as multiprocessing, telecommunications, data communications, cable systems, set top boxes, etc. The chip can implement features such as backplane communication, hot docking, cable diagnostics, etc.
The X5114 makes extensive use of nonvolatile memory with 4,096 bits of general purpose EEPROM, nonvolatile configuration registers, and nonvolatile programming of the port pins. The ports can be set up as sixteen general I/Os with pin selectable data direction (including eight inputs with nonvolatile threshold selections) or as an eight bit port with handshake. The chip is controlled via two redundant 2MHz SPI serial ports.
A sophisticated interrupt controller provides notification of a failed SPI command, changing conditions on an input, handshake status, and I/O errors. Interrupts are maskable.
On-chip EEPROM provides nonvolatile storage of system status, manufacturing information, board ID or other parameters.