X2804A

The X2804A has the following features including Reliable N-Channel Floating Gate MOS Technology;Single 5V Supply;High Reliability:-Endurance: 10,000 Writes Per Byte,-Data Retention: 100 Years;Byte Write Time: 10 ms Max;Fast Access Time: 250 ns Max;Low Power Dissipation:-Active Current: 80 mA Max,-Standby Current: 50 mA Max.

The Xicor X2804A is a 512 x 8 E2PROM, fabricated with the same reliable N-channel floating gate MOS technology used in all Xicor 5V programmable nonvolatile memories. The X2804A is compatible with the JEDEC approved pinout for byte-wide memories.Xicor E2PROMs are designed and tested for applicayions requiring extended endurance and data retention.Endurance is specified as 10,000 cycles per byte minimum and data retention is specified as 100 years minimum.  Refer to Xicor reliability reports RR-520 and RR-515 for details of endurance and data retention characteristics.Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and the functional these or any other conditions above operation of the device at those indicated in the erational sections of this specificstion is not implied.Exposure to absolute maximum rating conanions for extenaea penoos may affect device reliability.

A byte write operation, once initiated, will automatically continue to completion, typically within 5 ms. In order to take advantage of the typical write time as opposed to the maximum specified time, the user can poll the X2804A. The I/O pins are placed in the high impedance state during the internal programming cycle. Once the internal cycle is complete, the X2804A may be accessed without any limitations. Therefore, the host can poll an address with known data (preferably with zeroes), as soon as a compare is true, the X2804A is ready for another write cycle.Because the X2804A is frequently used in large memory arrays it is provided with a two line control architeclure for both read and write operations. Proper usage can provide the lowest possible power dissipation and eliminate the possibility of contention where multiple I/O pins share the same bus.