WMF512K8-XXX5

· Access Times of 60, 70, 90, 120, 150ns
· Packaging
• 32 pin, Hermetic Ceramic, 0.600" DIP (Package 300)
• 32 lead, Hermetic Ceramic, 0.400" SOJ (Package 101)
• 32 pin, Rectangular Ceramic Leadless Chip Carrier (Package 601)
• 32 lead Flatpack (Package 220)
· 1,000,000 Erase/Program Cycles Minimum
· Sector Erase Architecture
• 8 equal size sectors of 64K bytes each
• Any combination of sectors can be concurrently erased. Also supports full chip erase
· Organized as 512Kx8
· Commercial, Industrial and Military Temperature Ranges
· 5 Volt Programming. 5V ± 10% Supply.
· Low Power CMOS
· Embedded Erase and Program Algorithms
· TTL Compatible Inputs and CMOS Outputs
· Page Program Operation and Internal Program
Control Time.

NOTES:
1. Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability.

2. Minimum DC voltage on input or I/O pins is -0.5V. During voltage transitions, inputs may overshoot VSS to -2.0 V for periods of up to 20ns. Maximum DC voltage on output and I/O pins is V_CC + 0.5V. During voltage transitions, outputs may overshoot to Vcc + 2.0 V for  eriods of up to 20ns.

3. Minimum DC input voltage on A9 pin is -0.5V. During voltage transitions, A9 may overshoot Vss to -2V for periods of up to 20ns. Maximum DC input voltage on A9 is +13.5V which may overshoot to 14.0 V for periods up to 20ns.