WI10256

Features: SpecificationsDescriptionThe WI10256 is a 256 bit solid state sensor which is part of a family of imaging devices odering a high level of performance. These devices consist of a linear array of 13 x 13 micron photodiodes; imaged signal information is transferred via high speed CCD shift ...

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SeekIC No. : 004545741 Detail

WI10256: Features: SpecificationsDescriptionThe WI10256 is a 256 bit solid state sensor which is part of a family of imaging devices odering a high level of performance. These devices consist of a linear arr...

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Part Number:
WI10256
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/12/21

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Product Details

Description



Features:






Specifications






Description

The WI10256 is a 256 bit solid state sensor which is part of a family of imaging devices odering a high level of performance. These devices consist of a linear array of 13 x 13 micron photodiodes; imaged signal information is transferred via high speed CCD shift registers to the output. And it possesses the features of high resolution / sensitivity, wide speciral response, very low dark currents, dynamic range typically 4000:1, simple TTL level clock interfaces. The WI10256 can be  used as measurement / positioxning systems, facsimile, bar code readers, discrete image analysis, character recognition.

The electrical specification of major parameters of WI10256 are supply voltage: --(min)/12(typ)/15(max)V, clock high level: 4.5/5.0/5.5V( ie. TTL. levels), dynamic range : 4000: 1(typ)(Sat. signal nms noise), max. output signal: 1.5V(typ), non-uniformity: 20 mV(typ)(Ims integration time), frequency: 15/20 MHz, responsivity 1(typ)V/uJ/cm2(400-1000nm wavelength).

The pin description for WI10256 are VDDA +15V (analogue) 1 transfer clock 1; Vgg output gate bias VSSD 0V (digital); VIG input gate bias T transfer (shutter) pulse; Vgm O/P buffer bias VDDD + 15V (digital); VCOMP compensation bias PD power down clock gen; VOUT output signal 2 transfer clock 2; VBB substrate bias NC not connected; VSSA oV (analogue) TTL, input TTL level clock; VABG anti-blooming bias VSTORE storaqe qate bias.






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