WED8L24513V

*Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

The WED8L24513VxxBC is a 3.3V, twelve megabit SRAM constructed with three 512Kx8 die mounted on a multi-layer laminate substrate. With 10 to 15ns access times, x24 width and a 3.3V operating voltage, the WED8L24513V is ideal for creating a single chip memory solution for the Motorola DSP5630x (Figure 7) or a two chip solution for the Analog Devices SHARCTM DSP (Figure 8).

The single or dual chip memory solutions offer improved system performance by reducing the length of board traces and the number of board connections compared to using multiple monolithic devices.

The JEDEC Standard 119 lead BGA of the WED8L24513V provides a 61% space savings over using three 512Kx8, 400 mil wide SOJs and the BGA package has a maximum height of 110 mils compared to 148 mils for the SOJ packages.