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WED3EG7233S-JD3

Features: · Double-data-rate architecture· DDR200 and DDR266 • JEDEC design specifi ed· Bi-directional data strobes (DQS)· Differential clock inputs (CK & CK#)· Programmable Read Latency 2,2.5 (clock)· Programmable Burst Length (2,4,8)· Programmable Burst type (sequential & interleav...

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SeekIC No. : 004545586 Detail

WED3EG7233S-JD3: Features: · Double-data-rate architecture· DDR200 and DDR266 • JEDEC design specifi ed· Bi-directional data strobes (DQS)· Differential clock inputs (CK & CK#)· Programmable Read Latency 2...

WED3EG7233S-JD3 Data Sheet

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Part Number:
WED3EG7233S-JD3
Supply Ability:
5000

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  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/12/22

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Product Details

Description



Features:

· Double-data-rate architecture
· DDR200 and DDR266
   • JEDEC design specifi ed
· Bi-directional data strobes (DQS)
· Differential clock inputs (CK & CK#)
· Programmable Read Latency 2,2.5 (clock)
· Programmable Burst Length (2,4,8)
· Programmable Burst type (sequential & interleave)
· Edge aligned data output, center aligned data input.
· Auto and self refresh
· Serial presence detect
· Dual Rank
· Power supply: 2.5V ± 0.20V
   · JEDEC standard 184 pin DIMM package
   • JD3 PCB height: 30.48mm (1.20")


Specifications

PARAMETER SYMBOL RATING UNTE
Voltage on any pin relative to Vss VIN, VOUT -0.5 to 3.6 V
Voltage on VCC supply relative to Vss VCC,VDDQ -0.1 to 3.6 V
Storage temperature TSTG -55 to +150
Power dissipation PD 18 W
Short circuit current IOS 50 mA

Note: Permanent device damage may occur if 'ABSOLUTE MAXIMUM RATINGS' are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability


Description

The WED3EG7233S-JD3 is a 2x16Mx72 Double Data Rate SDRAM memory module based on 128Mb DDR SDRAM component. The module consists of eighteen 16Mx8 DDR SDRAMs in 66 pin TSOP packages mounted on a 184 pin FR4 substrate.

Synchronous design of the WED3EG7233S-JD3 allows precise cycle control with the use of system clock. Data I/O transactions are possible on both edges and Burst Lengths allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.




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