WED3EG7232S-JD3

Features:

·  Double-data-rate architecture
·  DDR200, DDR266, DDR333 amd DDR400
     • JEDEC design specifi cations
·  Bi-directional data strobes (DQS)
·  Differential clock inputs (CK & CK#)
·  Programmable Read Latency 2, 2.5 (clock)
·  Programmable Burst Length (2, 4, 8)
·  Programmable Burst type (sequential & interleave)
·  Edge aligned data output, center aligned data input.
· Auto and self refresh
·  Serial presence detect
·  Power supply:
     • V_CC = V_CCQ = +2.5V ± 0.2V (100, 133 and 166MHz)
     • V_CC = V_CCQ = +2.6V ± 0.1V (200MHz)
·JEDEC 184 pin DIMM package
     • JD3 PCB height: 30.48 (1.20") Max


Specifications

Parameter	Symbol	Value	Unit
Voltage on any pin relative to VSS	VIN, VOUT	-0.5 to 3.6	V
Voltage on VCC supply relative to VSS	VCC, VCCQ	-1.0 to 3.6	V
Storage Temperature	TSTG	-55 to +150
Power Dissipation	PD	9	W
Short Circuit Current	IOS	50	mA

Note: Permanent device damage may occur if 'ABSOLUTE MAXIMUM RATINGS' are exceeded.
          Functional operation should be restricted to recommended operating condition.
          Exposure to higher than recommended voltage for extended periods of time could affect device reliability


Description

The WED3EG7232S-JD3 is a 32Mx72 Double Data Rate SDRAM memory module based on 256Mb DDR SDRAM components. The module consists of nine 32Mx8 DDR SDRAMs in 66 pin TSOP packages mounted on a 184 pin FR4 substrate.

Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions of the WED3EG7232S-JD3 are possible on both edges and Burst Lengths allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.