Features: 40% Space Savings vs. Monolithic Solution Reduced System Inductance and Capacitance3.3V Operating Supply Voltage Fully Synchronous to Positive Clock Edge Clock Frequencies of 100MHz - 133MHz Burst Operation• Sequential or Interleave• Burst Length = Programmable 1, 2, 4, 8or ...
WED3DL3216V: Features: 40% Space Savings vs. Monolithic Solution Reduced System Inductance and Capacitance3.3V Operating Supply Voltage Fully Synchronous to Positive Clock Edge Clock Frequencies of 100MHz - 133...
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Features: Footprint compatible with WED3C7558M-XBX and WED3C750A8M-200BXImplementation of AltivecT...
Features: · Footprint compatible with WED3C7410E16M-XBX, WED3C7558M-XBX and WED3C750A8M-200BX· Imp...
Features: * Footprint compatible with WED3C7558M-XBX and WED3C750A8M-200BX* Implementation of Alti...
Parameter | Symbol | Min | Max | Units |
Power Supply Voltage | VCC/VCCQ | -1.0 | +4.6 | V |
Input Voltage | VIN | -1.0 | +4.6 | V |
Output Voltage | VOUT | -1.0 | +4.6 | V |
Operating Temperature | TOPR | -0 | +70 | |
Storage Temperature | TTSG | -55 | +125 | |
Power Dissipation | PD | - | 1.5 | W |
Short Circuit Output Current | IOS | - | 50 | mA |
* Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specifi cation is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
The WED3DL3216V is an 16Mx32 Synchronous DRAM confi gured as 4x4Mx32. The SDRAM BGA is constructed with two 16Mx16 SDRAM die mounted on a multi-layer laminate substrate and packaged in a 119 lead, 17mm by 23mm, BGA.
The WED3DL3216V is available in clock speeds of 133MHz, 125MHz, and 100MHz. The range of operating frequencies, programmable burst lengths and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.
The package and design of the provides performance enhancements via a 50% reduction in capacitance vs.
two monolithic devices. The design includes internal ground and power planes which reduces inductance on the ground and power pins allowing for improved decoupling and a reduction in system noise.