Features: · Double-data-rate architecture· Bi-directional data strobes (DQS)· Differential clock inputs (CK & CK#)· Programmable Read Latency 2,2.5 (clock)· Programmable Burst Length (2,4,8)· Programmable Burst type (sequential & interleave)· Edge aligned data output, center aligned data i...
WED3DG6417S: Features: · Double-data-rate architecture· Bi-directional data strobes (DQS)· Differential clock inputs (CK & CK#)· Programmable Read Latency 2,2.5 (clock)· Programmable Burst Length (2,4,8)· Pr...
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Features: Footprint compatible with WED3C7558M-XBX and WED3C750A8M-200BXImplementation of AltivecT...
Features: · Footprint compatible with WED3C7410E16M-XBX, WED3C7558M-XBX and WED3C750A8M-200BX· Imp...
Features: * Footprint compatible with WED3C7558M-XBX and WED3C750A8M-200BX* Implementation of Alti...
Parameter | Symbol | Value | Units |
Voltage on any pin relative to VSS | VIN, VOUT | -0.5 ~ 3.6 | V |
Voltage on VCC supply relative to VSS | VCC, VCCQ | -1.0 ~ 3.6 | V |
Storage Temperature | TSTG | -55 ~ +150 | |
Power Dissipation | PD | 8 | W |
Short Circuit Current | IOS | 50 | mA |
Note:
Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
The WED3DG6417S is a 16Mx64 Double Data Rate SDRAM memory module based on 128Mb DDR SDRAM component. The module consists of eight 16Mx8 DDR SDRAMs in 66 pin TSOP package mounted on a 200 pin FR4 Substrate.
Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are possible on both edges and Burst Lenths allow the WED3DG6417S to be useful for a variety of high bandwidth, high performance memory system applications.