WD76C30

The WD76C30 device provides three functional groups. It is a Peripheral Controller, Interrupt Multiplexer, and Clock Generator.The low power CMOS WD76C30 is a single device solution which provides interrupt multiplexing logic,clock generation, two serial ports, and one bidirectional parallel port.

Features of the WD76C30 are:(1)built-in testability features; (2)hardware or software controllable sleep mode; (3)CMOS implementation for high speed and low power requirements; (4)pulse extension on IRQ inputs; (5)84-pin PLCC and PQFP packages; (6)parallel port configurable as a fully centronics or PS/2 compatible, bidirectional parallel port; (7)independently programmable parallel port.A software reset is performed by writing to the Divisor Latches, forcing the transmitter and receiver to an idle mode. Registers are not reset by this operation.  Prior to enabling interrupts, the LSR and RBR registers should be read to clear out any data, returning them to a known state without resetting the system.

The absolute maximum ratings of the WD76C30 can be summarized as:(1)all input or output voltages with respect to Vss:-0.3 to 7.0V;(2)storage temperature:-65 to 150;(3)power dissipation:300mW;(4)temperature under bias:0 to 70.The internal registers used for the interrupt multiplexing, clock selection and mode selection are accessed in a two step process, using two address locations in the Parallel Port Register.  First, the address for the desired register to be accessed is written into the Address Select Register located at address three of the Parallel Port. Then the data to be read from or written to the selected register is accessed through the Data Access Register (see Table 4-1),located at address seven in the Parallel Port. It is not necessary for these write operations to follow each other.The RCVR FIFO has an internal pointer that automatically points to the RCVR Data byte and associated Status byte to be read.  Reading the RCVR Data byte increments the internal counter,while reading the Status byte does not, therefore,the Status byte should always be read prior to reading the Data byte associated with it.