WCSS0418V1P

Storage Temperature ..............................-65 to +150
Ambient Temperature with
Power Applied..........................................-55 to +125
Supply Voltage on V_DD Relative to GND.....-0.5V to +4.6V
DC Voltage Applied to Outputs
in High Z State^[7] .............................-0.5V to V_DD + 0.5V
DC Input Voltage^[7] ..........................-0.5V to V_DD + 0.5V
Current into Outputs (LOW)...................................20 mA
Static Discharge Voltage..................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current.............................................. >200 mA

The WCSS0418V1P is a 3.3V, 256K by 18 synchronous-pipe-lined cache SRAM designed to support zero wait state sec-ondary cache with minimal glue logic.

The WCSS0418V1P I/O pins can operate at either the 2.5V or the 3.3V level. The I/O pins are 3.3V tolerant when V_D-DQ=2.5V.

All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs of WCSS0418V1P pass through output registers controlled by the rising edge of the clock. Maximum access delay from the clock rise is 3.5 ns (166-MHz device).

The WCSS0418V1P supports either the interleaved burst sequence used by the Intel Pentium processor or a linear burst sequence used by processors such as the PowerPC. The burst sequence is selected through the MODE pin. Accesses can be initiated by asserting either the Processor Address Strobe (ADSP) or the Controller Address Strobe (ADSC) at clock rise. Address advancement through the burst sequence  is controlled by the ADV input. A 2-bit on-chip wraparound burst counter captures the first address in a burst sequence and automatically increments the address for the rest of the burst access.

Byte write operations of WCSS0418V1P are qualified with the four Byte Write Select (BW_[1:0]) inputs. A Global Write Enable (GW) overrides all byte write inputs and writes data to all four bytes. All writes are conducted with on-chip synchronous self-timed write circuitry.