W982504BH

W982504BH is a high-speed synchronous dynamic random access memory (SDRAM), organized as 8M words x 4 banks x 4 bits. Using pipelined architecture and 0.20um process technology, W982504BH delivers a data bandwidth of up to 133M (-75) words per second. To fully comply with the personal computer industrial standard, W982504BH is sorted into two speed grades: -75 and -8H. The -75 is compliant to the PC133/CL3 specification. The -8H is compliant to the PC100/CL2 specification.

Accesses to the SDRAM are burst oriented. Consecutive memory location in one page can be accessed at a burst length of 1, 2, 4, 8 or full page when a bank and row is selected by an ACTIVE command. Column addresses are automatically generated by the SDRAM internal counter in burst operation. Random column read is also possible by providing W982504BH's address at each clock cycle. The multiple bank nature enables interleaving among internal banks to hide the precharging time.

By having a programmable Mode Register, the system can change burst length, latency cycle, interleave or sequential burst to maximize its performance. W982504BH is ideal for main memory in high performance applications.