W946432AD

The W946432AD is a high-speed CMOS Double Data Rate synchronous dynamic random access memory organized as 512K words x 4 banks x 32 bits.

A bidirectional data strobe (DQS) is transmitted externally, along with data, for use in data capture at the receiver. DQS is a strobe transmitted by the DDR SDRAM W946432AD during READs and by the memory controller during WRITEs. DQS is edge-aligned with data for READs and center-aligned with data for WRITEs.
The W946432AD operates from a differential clock (CLK and CLK the crossing of CLK W946432AD going HIGH and CLK going LOW will be referred to as the postive edge of CLK). Commands (address and control signals) are registered at every positive edge of CLK. Input data of W946432AD is registered on both edges of DQS, and output data is referenced to both edges of DQS, as well as to both edges of CLK.

Read and write accesses to the DDR SDRAM W946432AD are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command W946432AD are used to select the bank and row to be accessed. The address bits registered coincident with the READ or WRITE command are used to select the bank and the starting column location for the burst access.

The DDR SDRAM W946432AD provides for programmable READ or WRITE burst lengths of 2, 4 or 8 locations. An AUTO PRECHARGE function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access.

As with standard SDRAMs, the pipelined, multibank architecture of DDR SDRAMs W946432AD allows for concurrent operation, thereby providing high effective bandwidth by hiding row precharge and activation time.