W93902

The W93902 is a very-low-power decoder for pagers that is fully compatible with CCIR Radio Paging Code Number 1 (POCSAG code) operating at 512, 1200, or 2400 bps using a single 76.8 KHz crystal. To enhance the sensitivity of the pager system, a digital filter and digital PLL W93902 have been incorporated to remove the noise factor generated by the RF part and lock the signal phase.

To reduce the RF W93902 turn-on time and minimize power consumption, an advanced synchronization algorithm (1/18 turn on-time, as opposed to 1/17 or 1/16) is used to provide synchronization. Synchronization skip mode is also available for power reduction.

For convenient pager programming, the decoder W93902 provides fully software-programmable options and a simple CPU control format (data output packaged as 4/7/8 bits or not packaged). Also included are independent buzzer and LED frequency control outputs and a reference clock (32768 Hz, 64 Hz, 16 Hz, 1/60 Hz) that can be output or disabled. The decoder W93902 supports four independent user addresses, which can be assigned to different frames.