Features: Architecture
· Fully 16/32-bit RISC architecture
· Little/Big-Endian mode supported
· Efficient and powerful ARM7TDMI core
· Cost-effective JTAG-based debug solution
External Bus Interface
· 8/16/32-bit external bus support for ROM/SRAM, flash memory, SDRAM and external I/Os
· Support for SDRAM
· Programmable access cycle (0-7 wait cycle)
· Four-word depth write buffer for SDRAM write data
· Cost-effective memory-to-peripheral DMA interface
Instruction and Data Cache
· Two-way, Set-associative, 4K-byte I-cache and 4K-byte D-cache
· Support for LRU (Least Recently Used) Protocol
· Cache can be configured as internal SRAM
· Support Cache Lock function
Ethernet MAC Controller
· DMA engine with burst mode
· MAC Tx/Rx buffers (256 bytes Tx, 256 bytes Rx)
· Data alignment logic
· Endian translation
· 100/10-Mbit per second operation
· Full compliance with IEEE standard 802.3
· RMII interface only
· Station Management Signaling
· On-Chip CAM (up to 16 destination addresses)
· Full-duplex mode with PAUSE feature
· Long/short packet modes
· PAD generation
LCD Controller (LCDC)
(1) STN LCD Display
· Supports 4-bit single scan Monochrome STN LCD panel, 8-bit single scan Monochrome STN LCD
panel, 8-bit single scan Color STN LCD panel
· Up to 16 gray levels display for Monochrome STN LCD panel
· Up to 4096(12bpp) colors display for Color STN LCD panel
· Virtual coloring method: Frame Rate Control (16-level)
· Anti-flickering method: Time-based Dithering
(2) TFT LCD Display
· Supports Sync-type TFT LCD panel and Sync-type High-color TFT LCD panel
· Supports direct or palettized color display
(3) TV Encoder
· Supports 8-bit YCbCr data output format to connect with external TV Encoder
(4) LCD Preprocessing
· Supports RGB Raw-data or packetd YUV422 format
· Programmable parameters for different image size
· Build in two FIFOs, FIFO 1 is for Video image and FIFO 2 is for OSD image. Each FIFO is 16 words deep
(5) LCD Post processing
· Support for one OSD (On-Screen-Display) overlay
· Support various OSD function
· Programmable parameters for different display panel
(6) Others
· Color-look up table size 256x32 bit for TFT used when displaying 1bpp, 2bpp, 4bpp, 8bpp image
· Dedicated DMA for block transfer mode
DMA Controller
· 2-channel General DMA for memory-to-memory data transfers without CPU intervention
· Initialed by a software or external DMA request
· Increments or decrements a source or destination address in 8-bit, 16-bit or 32-bit data transfers
· 4-data burst mode
UART
· Four UART (serial I/O) blocks with interrupt-based operation
· Support for 5-bit, 6-bit, 7-bit or 8-bit serial data transmit and receive
· Programmable baud rates
· 1, ½ or 2 stop bits
· Odd or even parity
· Break generation and detection
· Parity, overrun and framing error detection
· X16 clock mode
· UART1 supports Bluetooth, and UART2 supports IrDA1.0 SIR
Timers
· Two programmable 24-bit timers with 8-bit pre-scaler
· One programmable 20 bit with selectable additional 8-bit prescaler Watchdog timer
· One-shot mode, periodical mode or toggle mode operation
Programmable I/Os
· 71 programmable I/O ports
· Pins individually configurable to input, output or I/O mode for dedicated signals
· I/O ports are configurable for Multiple functions
Advanced Interrupt Controller
· 31 interrupt sources, including 6 external interrupt sources
· Programmable normal or fast interrupt mode (IRQ, FIQ)
· Programmable as either edge-triggered or level-sensitive for 6 external interrupt sources
· Programmable as either low-active or high-active for 6 external interrupt sources
· Priority methodology is encoded to allow for interrupt daisy-chaining
· Automatically mask out the lower priority interrupt during interrupt nesting
USB Host Controller
· USB 1.1 compliant
· Compatible with Open HCI 1.0 specification
· Supports low-speed and full speed devices
· Build-in DMA for real time data transfer
· Two on-chip USB transceivers with one optionally shared with USB Device Controller
USB Device Controller
· USB 1.1 compliant
· Support four USB endpoints including one control endpoint and 3 configurable endpoints for rich
USB functions
Two PLLs
· The external clock can be multiplied by on-chip PLL to provide high frequency system clock
· The input frequency range is 3-30MHz; 15MHz is preferred.
· One PLL for both CPU and USB host/device controller
· One PLL for LCD pixel clock and audio IIS 12.288/16.934MHz clock source
· Programmable clock frequency
Real Time Clock (RTC)
· 32.768KHz operation
· Time counter (second, minute, hour) and calendar counter (day, month, year)
· Alarm register (second, minute, hour, day, month, year)
· 12 or 24-hour mode selectable
· Recognize leap year automatically
· Day of the week counter
· Frequency compensate register (FCR)
· Beside FCR, all clock and alarm data expressed in BCD code
· Support tick time interrupt
4-Channel PWM
· Four 16-bit timers with PWM
· Two 8-bit pre-scalers & Two 4-bit dividers
· Programmable duty control of output waveform
· Auto reload mode or one-shot pulse mode
· Dead-zone generator
I2C Master
· Two Channel I2C
· Compatible with Philips I2C standard, support master mode only
· Support multi master operation
· Clock stretching and wait state generation
· Provide multi-byte transmit operation, up to 4 bytes can be transmitted in a single transfer
· Software programmable acknowledge bit
· Arbitration lost interrupt, with automatic transfer cancellation
· Start/Stop/Repeated Start/Acknowledge generation
· Start/Stop/Repeated Start detection
· Bus busy detection
· Supports 7 bit addressing mode
· Software mode I2C
Universal Serial Interface (USI)
· 1-Channel USI
· Support USI (Microwire/SPI) master mode
· Full duplex synchronous serial data transfer
· Variable length of transfer word up to 32 bits
· Provide burst mode operation, transmit/receive can be executed up to four times in one transfer
· MSB or LSB first data transfer
· Rx and Tx on both rising or falling edge of serial clock independently
· Two slave/device select lines
· Fully static synchronous design with one clock domain
2-Channel AC97/I2S Audio Codec Host Interface
· AHB master port and an AHB slave port are offered in audio controller.
· Always 8-beat incrementing burst
· Always bus lock when 8-beat incrementing burst
· When reach middle and end address of destination address, a DMA_IRQ is requested to CPU
automatically
Smart Card Host Interface (SCHI)
· ISO-7816 compliant
· PC/SC T=0, T=1 compliant
· 16-byte transmitter FIFO and 16-byte receiver FIFO
· FIFO threshold interrupt to optimize system performance
· Programmable transmission clock frequency
· Versatile baud rate configuration
· UART-like register file structure
· General-purpose C4, C8 channels
SD Host Interface
· Directly connect to Secure Digital (SD, MMC) flash memory card.
· Supports DMA function to accelerate the data transfer between the internal buffer, external
SDRAM, and flash memory card.
· Two 512 bytes internal buffers are embedded inside the controller.
· No SPI mode.
KeyPad Scan Interface
· Scan up to 16 rows by 8 columns with an external 4 to 16 decoder and 4 rows by 8 columns array
without auxiliary component
· Programmable debounce time
· One or two keys scan with interrupt and three keys reset function.
· Wakeup CPU from IDEL/Power Down mode
PS2 Host Interface
· APB slave consisted of PS2 protocol.
· Connect IBM keyboard or bar-code reader through PS2 interface.
· Provide hardware scan code to ASCII translation
Power management
· Programmable clock enables for individual peripheral
· IDLE mode to halt ARM Core and keep peripheral working
· Power-Down mode to stop all clocks included external crystal oscillator.
· Exit IDLE by all interrupts
· Exit Power-Down by keypad,USB device and external interrupts
Operation Voltage Range
· 3.0 ~ 3.6 V for IO Buffer
· 1.62 ~ 1.98 V for Core Logic
Operation Temperature Range
· TBD
Operating Frequency
· Up to 80 MHz
Package Type
· 176-pin LQFPPinout
SpecificationsAmbient temperature ........................................................... TBD
Storage temperature .......................................-40 °C ~ +125°C
Voltage on any pin .....................................................-0.5V ~ 6V
Power supply voltage (Core logic) ....................... -0.5V ~ 1.92V
Power supply voltage (IO Buffer) .......................... -0.5V ~ 3.6V
Injection current (latch-up testing) ................................ 100mA
Crystal Frequency ..............................................4MHz ~ 30MHzDescriptionThe W90P710 is built around an outstanding CPU core, the 16/32 ARM7TDMI RISC processor which designed by Advanced RISC Machines, Ltd. It offers 4K-byte I-cache/SRAM and 4K-byte Dcache/ SRAM, is a low power, general purpose integrated circuits. Its simple, elegant, and fully static design W90P710 is particularly suitable for cost sensitive and power sensitive applications.
One 10/100 Mb MAC of Ethernet controller W90P710 is built-in to reduce total system cost. A LCD controller is also built-in to support TFT and low cost STN LCD modules.
With one USB 1.1 host controller, one USB 1.1 device controller, two smart card host controller, four independent UARTs, one Watchdog timer, up to 71 programmable I/O ports, PS/2 keyboard controller and an advanced interrupt controller, the W90P710 is particularly suitable for point-of-sale (POS), access control and data collector.
The W90P710 also provides one AC97/I²S controller, one SD host controller, one 2-Channel GDMA, two 24-bit timers with 8-bit pre-scale, The external bus interface (EBI) controller provides for SDRAM, ROM/SRAM, flash memory and I/O devices. The System Manager W90P710 includes an internal 32-bit system bus arbiter and a PLL clock controller. With a wide range of serial communication and Ethernet interfaces, the W90P710 is also suitable for communication gateways as well as many other general purpose applications.
W90P710CD Data Sheet
