Features: ·2 pair 0.7 V current mode Differential clock outputs for CPU ·6 pair 0.7V current mode Differential clock outputs for SRC and SRC_SATA. ·1 pair 0.7V current mode Differential 96MHz clock outputs for DOT.· 6 PCI clock outputs for PCI ·3 PCI clock free running outputs for PCI ·1 48 MHz cl...
W83195BR/G-101: Features: ·2 pair 0.7 V current mode Differential clock outputs for CPU ·6 pair 0.7V current mode Differential clock outputs for SRC and SRC_SATA. ·1 pair 0.7V current mode Differential 96MHz clock ...
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These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales.
Parameter |
Rating |
Absolute 3.3V Core Supply Voltage Absolute 3.3V I/O Supple Voltage Operating 3.3V Core Supply Voltage Operating 3.3V I/O Supple Voltage Storage Temperature Ambient Temperature Operating Temperature Input ESD protection (Human body model) |
-0.5V to +4.6V - 0.5V to + 4.6V 3.135V to 3.465V 3.135V to 3.465V - 65 to + 150 - 55 to + 125 0 to + 70 2000V |
The W83195BR/G-101 is a Clock Synthesizer for Intel P4 processors and Intel Grandsdale chipsets. W83195BR/G-101 provides all clocks required for high-speed microprocessor and provides step-less frequency programming, 32 different frequencies of CPU, PCI, SRC clocks setting. Simultaneously W83194BR-101 supports SRC_SATA 100MHz clock output for SATA and DOT 96MHz clock outputs for integrated graphic chipsets. All clocks are externally selectable with smooth transitions.
The W83195BR/G-101 programs the registers to enable or disable each clock outputs through I2C serial bus interface and provides -0.5% down type spread spectrum or programmable spread spectrum scale to reduce EMI.
The W83195BR/G-101 is driven with a 14.318 MHz reference crystal and runs on a 3.3V supply.