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W83178S

Features: · Supports Intel Pentium II CPUs for BX chipset· 13 SDRAM clocks for 3-DIMMs· Clock skew less than 250 pS· Almost none delay Buffer-in controlling SDRAM clocks(<4 nS propagation delay)· I2C 2-wire serial interface· Programmable registers to enable/stop each output· Incorporate with W8...

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SeekIC No. : 004545091 Detail

W83178S: Features: · Supports Intel Pentium II CPUs for BX chipset· 13 SDRAM clocks for 3-DIMMs· Clock skew less than 250 pS· Almost none delay Buffer-in controlling SDRAM clocks(<4 nS propagation delay)·...

W83178S Data Sheet

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Part Number:
W83178S
Supply Ability:
5000

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  • 1~5000
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Product Details

Description



Features:

· Supports Intel Pentium II CPUs for BX chipset
· 13 SDRAM clocks for 3-DIMMs
· Clock skew less than 250 pS
· Almost none delay Buffer-in controlling SDRAM clocks(<4 nS propagation delay)
· I2C 2-wire serial interface
· Programmable registers to enable/stop each output
· Incorporate with W83196S-14
· Packaged in 28-pin SOP


Pinout

Connection Diagram


Specifications

PARAMETER SYMBOL RATING
Voltage on any pin with respect to GND VDD, VIN -0.5V to +7.0V
Storage Temperature TSTG -65° C to +150° C
Ambient Temperature TB -55° C to +125° C
Operating Temperature TA 0° C to +70° C
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device.


Description

 

The W83178S is a 13 outputs SDRAM clock buffer for 3-DIMMs models incorporate with W83196S- 14 which is the clock synthesizer especially for the 100 MHz models such as Intel BX chipsets. (Refer the datasheet fo Winbond W83196S-14)

The W83178S receives the clock from chipset by the Buffer_In pin and provides almost zero-delay (less than 4 nS propagation delay) SDRAM buffer outputs for the 13 SDRAM clocks which are synchronous with the CPU clock outputs priovided by W83196S-14. The clock skew between any two clock outputs is less than 250 pS and the output buffer impedance is about 15 ohms.

The W83178S also provides I2C serial bus interface to program the registers to enable or disable each SDRAM clock outputs.




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