W764M32V

NOTES: 1. Minimum DC voltage on input or input or I/Os is -0.5V. During voltage transitions, inputs or I/Os may overshoot VSS to -2.0V for periods of up to 20ns. Maximum DC voltage on input or I/Os us VCC + 0.5V. During voltage transitions, input or I/O pins may overshoot to VCC + 2.0V for periods up to 20ns

2. Minimum DC input voltage on pins A9, OE#, and ACC is 0.5V. During voltage transitions, A9, OE#, and ACC may overshoot VSS to -2.0V for periods of up to 20ns. Maximum DC input voltage on pin A9, OE#, and ACC is +12.5V which may overshoot to +14.0V for periods up to 20ns

3. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater than one second. 4. Stresses above those listed under Absolute Maxium Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of the data sheet is not implied. Exposure of the device to absolute maxium rating conditons for extended peroids may affect device reliability

The W764MB2V-XSBX device is a 3.0V single power flash memory. The device utilizes four organized as 33,554,432 words or 67, 108,864 bytes. The device has 64 -bit wide data bus that can also function as an 32-bit wide data bus by using the BYTE# input. The device can be programmed either in the host system or in standard EPROM programmers. Each device requires a single 3.0 volt power supply for both read and write functions.

In addition to a VCC input, an high-voltage accelerated program (WP / ACC) input provides shorter programming times through increased current. This feature is intended to facilitate factory throughput during system production, but may also be used in the fi eld if desired. The devices are entirely command set compatible with the JEDEC single power-supply Flash standard. Commands are written to the device using standard microprocessor write timing. Write cycles also internally latch addresses and data needed for the programming and erase operations.

The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory. Device programming and erasure are initiated through command sequences. Once a program or erase operation has begun, the host system need only poll the DQ7 (Data# Polling) or DQ6 (toggle) status bits or monitor the Ready / Busy# (RY / BY#) output to determine whether the operation is complete. To facilitate programming, an Unlock Bypass mode reduces command sequence over head by requiring only two write cycles to program data instead of four.

The I/O (VIO) control allows the host system to set the voltage levels that the device generates and tolerates on all input levels (address, chip control, and DQ input levels) to the same voltage level that is asserted on the VIO pin. This allows the device to operate in a 1.8 V or 3 V system environment as required. Hardware data protection measures include a low VCC detector that automatically inhibits write operations during power transitions. Persistent Sector Protection provides in-system, comand-enabled protection of any combination of sectors using a single power supply at VCC.

Password Sector Protection prevents unauthorized write and erase operations in any combination of sectors through a userde fi ned 64-bit password. The erase Suspend / Erase Resume feature allows the host system to pause and erase operation in a given sector to read or program any other sector and then complete the erase operation. The Program Suspend / Program Resume feature enables the host system to pause the program operation in a given sector to read any other sector and then complete the program operation. The hardware RESET# pin terminates any operation in progress and resets the device, after which it is then ready for a new operation.

The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the host system to read boot-up fi rmware from the Flash memory device. The device reduces power consumption in the standby mode when it detects specifi c voltage levels on CS# and RESET#, or when addresses have been stable for a specifi ed period of time.

The Secured Silicon Sector provides a 128-work/256-byte area for code or data that can be permanently protected. Once this sector is protected, no further changes within the sector can occur.

The Write Protect (WP# / ACC) feature protects the fi rst or last sector by asserting a logic low on the WP# pin.