W48C55A

The Functional Block Diagram shows the reference clock source can be a crystal connected across the X1 and X2 input pins, alternatively input clock connected to the X1 input pin. In the latter case, the X2 pin is left open. With either source as reference, both the W48C54A and W48C55A generate all necessary clocks at their respective frequencies to drive the specified clocks. To provide the broadest possible range of frequencies typically required for CPU mother-board designs, the target frequencies can be selected via up to four select inputs.

Consult the appropriate tables for the clock selection range. In addition, the W48C54A/55A can provide rebuffered reference clock outputs.

Both the W48C54A and W48C55A offer smooth transitions when changing CPU/2XCPU output frequency. This feature can best be used by power management systems where it is frequently necessary to slow down the clock to conserve power.

By controlling the rate of frequency transition, both devices are designed to be compatible with Intel® cycle-to-cycle processor timing specifications.

Power down capability is available in selected versions of the W48C54A and W48C55A. When PD is active (LOW), the device is placed in a standby mode during which power dissipation is at its minimum; all clock outputs are forced LOW. Partial power is also an available option, wherein selected outputs are disabled or enabled according to a logic input.