W42C31-03A

The W42C31-03A uses a phase-locked loop (PLL) to frequency modulate an input clock. The result is an output clock whose frequency is slowly swept over a narrow band near the input signal. The basic circuit topology is shown in Figure 1. An on-chip crystal driver causes the crystal to oscillate at its fundamental.

The resulting reference signal W42C31-03A is divided by Q and fed to the phase detector. A signal from the VCO is divided by P and fed back to the phase detector also. The PLL will force the frequency of the VCO output signal to change until the divided output signal and the divided reference signal match at the phase detector input. The output frequency is then equal to the ratio of P/Q times the reference frequency. The unique feature of the Spread Spectrum Clock Generator is that a modulating waveform is superimposed at the input to the VCO.

This causes the VCO output to be slowly swept across a predetermined frequency band.

Because the modulating frequency is typically 1000 times slower than the fundamental clock, the spread spectrum process has little impact on system performance.

In Spread Spectrum Frequency Timing Generation, EMI reduction depends on the shape, modulation percentage, and frequency of the modulating waveform. While the shape and frequency of the modulating waveform are fixed, the modulation percentage may be varied.

Using frequency select bits (FS1:0 pins), various spreading percentages can be chosen (see Table 1).

A larger spreading percentage improves EMI reduction. However, large spread percentages may either exceed system maximum frequency ratings or lower the average frequency to a point where performance is affected. For these reasons, spreading percentages between ±0.5% and ±2.5% are most common.

The W42C31 features the ability to select from various spread spectrum characteristics. Selections specific to the W42C31-03A are shown in Table 1. Other spreading characteristics are available (see separate data sheets) or can be created with a custom mask.