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W3EDG6465S

Features: · Double-date-rate architecture· DDR200 and DDR266• JEDEC design specifi cation· Bi-directional data strobes (DQS)· Differential clock inputs (CK CK#)· Programmable Read Latency 2, 2.5 (clock)· Programmable Burst Length (2,4,8)· Programmable Burst type (sequential & interactive...

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SeekIC No. : 004544680 Detail

W3EDG6465S: Features: · Double-date-rate architecture· DDR200 and DDR266• JEDEC design specifi cation· Bi-directional data strobes (DQS)· Differential clock inputs (CK CK#)· Programmable Read Latency 2, 2...

W3EDG6465S Data Sheet

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Part Number:
W3EDG6465S
Supply Ability:
5000

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  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

· Double-date-rate architecture
· DDR200 and DDR266
• JEDEC design specifi cation
· Bi-directional data strobes (DQS)
· Differential clock inputs (CK CK#)
· Programmable Read Latency 2, 2.5 (clock)
· Programmable Burst Length (2,4,8)
· Programmable Burst type (sequential & interactive)
· Edge aligned data output, center aligned data input
· Auto and self refresh
· Serial presence detected
· Power supply: 2.5V ± 0.20V
· standard 184 pin DIMM package
• Package height option: D3: 30.48mm (1.20")


Specifications

Parameter Symbol Value Units
Voltage on any pin relative to VSS VIN, VOUT -0.5 to 3.6 V
Voltage on VCC supply relative to VSS VCC, VCCQ -1.0 to 3.6 V
Storage Temperature TSTG -55 to +150
Power Dissipation PD 16 W
Short Circuit Current IOS 50 mA

Note: Permanent device damage may occur if 'ABSOLUTE MAXIMUM RATINGS' are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability




Description

The W3EDG6465S is a 64Mx64 Double Data Rate SDRAM memory module based on 128Mb DDR SDRAM components. The module consists of sixteen 64Mx4 DDR SDRAMs in 66 pin TSOP packages mounted on a 184 pin FR4 substrate.

Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are possible on both edges and Burst Lengths allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.




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