Features: Registered for enhanced performance of bus speeds of 200, 225, and 250 MHz
Package:
• 219 Plastic Ball Grid Array (PBGA), 32 x 25mm
2.5V ±0.2V core power supply
2.5V I/O (SSTL_2 compatible)
Differential clock inputs (CK and CK#)
Commands entered on each positive CK edge
Internal pipelined double-data-rate (DDR) architecture; two data accesses per clock cycle
Programmable Burst length: 2,4 or 8
Bidirectional data strobe (DQS) transmitted/ received with data, i.e., source-synchronous data capture (one per byte)
DQS edge-aligned with data for READs; centeraligned with data for WRITEs
DLL to align DQ and DQS transitions with CK
Four internal banks for concurrent operation
Two data mask (DM) pins for masking write data
Programmable IOL/IOH option
Auto precharge option
Auto Refresh and Self Refresh Modes
Commercial, Industrial and Military Temperature Ranges
Organized as 16M x 72
Weight: W3E16M72SR-XBX - 2.5 grams typicalSpecifications
| Parameter |
|
Unit |
| Voltage on VCC, VCCQ Supply relative to Vss |
-1 to 3.6 |
V |
| Voltage on I/O pins relative to VSS |
-1 to 3.6 |
V |
| Operating Temperature TA (Mil) |
-55 to +125 |
|
| Operating Temperature TA (Ind) |
-40 to +85 |
|
| Storage Temperature, Plastic |
-55 to +125 |
|
NOTE: Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions greater than those ndicated in the operational sections of this specifi cation is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability
DescriptionThe 128MByte (1Gb) DDR SDRAM is a high-speed CMOS, dynamic random-access, memory using 5 chips containing 268,435,456 bits. Each chip is internally confi gured as a quad-bank DRAM. Each of the chip's 67,108,864-bit banks is organized as 8,192 rows by 512 columns by 16 bits.
The 128 MB DDR SDRAM uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 2n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the 128MB DDR SDRAM effectively consists of a single 2n-bit wide, one-clock-cycle data tansfer at the internal DRAM core and two corresponding n-bit wide, one-half-clock-cycle data transfers at the I/O pins.
A bidirectional data strobe (DQS) is transmitted externally, along with data, for use in data capture at the receiver. DQS is a strobe transmitted by the DDR SDRAM during READs and by the memory contoller during WRITEs. DQS is edgealigned with data for READs and center-aligned with data for WRITEs. Each chip has two data strobes, one for the lower byte and one for the upper byte.
The 128MB DDR SDRAM operates from a differential clock (CK and CK#); the crossing of CK going HIGH and CK# going LOW will be referred to as the positive edge of CK.
Commands (address and control signals) are registered at every positive edge of CK. Input data is registered on both edges of DQS, and output data is referenced to both edges of DQS, as well as to both edges of CK.
Read and write accesses to the DDR SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed. The address bits registered coincident with the READ or WRITE command are used to select the bank and the starting column location for the burst access.
The DDR SDRAM provides for programmable READ or WRITE burst lengths of 2, 4, or 8 locations. An auto precharge function may be enabled to provide a selftimed row precharge that is initiated at the end of the burst access.
The pipelined, multibank architecture of DDR SDRAMs allows for concurrent operation, thereby providing high effective bandwidth by hiding row precharge and activation time.
An auto refresh mode is provided, along with a powersaving power-down mode.
W3E16M72SR-XBX Data Sheet
