W332M64V-XBX

The 256MByte (2Gb) SDRAM W332M64V-XBX is a high-speed CMOS,dy nam ic ran dom-access, memory using 4 chips ontaining ,870,912 bits. Each chip is internally con gured as a quad-bank DRAM with a syn chro nous interface. Each of the chips ,217,728-bit banks is orga nized as 8,192 rows by 1,024 columns by 16 bits.

Read and write accesses to the SDRAM W332M64V-XBX are burst oriented; ac cess es start at a selected location and continue for a pro grammed number of locations in a programmed se quence. Ac cess es be gin with the registration of an ACTIVE com nd, which is then fol lowed by a READ or WRITE com mand. The address bits reg is tered coincident with the AC TIVE mand are used to select the bank and row to be accessed (BA0, BA1 select the bank; A012 select the row). The address bits reg is tered co in ci dent with the READ or WRITE com mand are used to se lect the starting col umn lo ca tion for the rst ac cess.

The SDRAM W332M64V-XBX provides for programmable READ or WRITE burst lengths of 1, 2, 4 or 8 locations, or the full page, with a rst terminate option. An AUTO PRECHARGE function may be en abled to provide a self-timed row precharge that is initiated at the end of the burst sequence.

The 2Gb SDRAM W332M64V-XBX uses an internal pipelined architecture to achieve high-speed operation. This architecture is com pat i le with the 2n rule of prefetch architectures, but it also allows the column ad dress to be changed on every clock cycle to e a high-speed, fully random access. Precharging one bank while ac cess ing one of the other three banks will hide the e cycles and provide seam less, highspeed, random-access op er a tion.