VT8501

• General
   − 492 BGA Package (35mm x 35mm )
   − 2.5 Volt +/- 0.2V Core
   − Supports separately powered 3.3V tolerant interface to CPU and Memory
   − Supports separately powered 5.0V tolerant interface to PCI bus and Video interface
   − 2.5V, 0.25um, high speed / low power CMOS process
   − PC-98/99 compatible using VIA VT82C686A (352-pin BGA) south bridge chip
   − 66 / 100 MHz Operation
• Socket 7 Host Interface
   − Supports all Socket-7 / Super-7 processors including 64-bit Intel Pentium™ / Pentium™ with MMX™ , AMD
      6K86™ (K6™ and K6-2™), Cyrix/IBM 6x86™ / 6x86MX™ , IDT/Centaur C6, and Rise MP6 CPUs
   − 66 / 100 MHz CPU "Front Side Bus"
   − Supports 3.3V and sub-3.3V interface to CPU
   − Built-in de-skew PLL (Phase Lock Loop) circuitry for optimal skew control within and between clocking regions
   − Cyrix/IBM 6x86™ linear burst support
   − AMD K6™ and K6-2™ write allocation support
   − Supports CPU-to-DRAM write combining
   − System management interrupt, memory remap and stop clock mechanisms
• Advanced L2 Cache
   − Direct map write-back or write-through secondary cache
   − Pipelined burst synchronous SRAM (PBSRAM) cache support
   − Flexible cache size: 0K / 256K / 512K / 1M / 2MB
   − 32 byte line size to match the primary cache
   − Integrated 8-bit tag comparator
   − 3-1-1-1-1-1-1-1 back to back read timing for PBSRAM accesses up to 100 MHz
   − Tag timing optimized (less than 4ns setup time) to allow external tag SRAM implementation for most flexible
      cache organization
   − Sustained 3 cycle write access for PBSRAM access or CPU to DRAM & PCI bus post write buffers up to 100 MHz
   − Supports CPU single read cycle L2 allocation
   − System and video BIOS cacheable and write-protect
   − Programmable cacheable region
• Internal Accelerated Graphics Port (AGP) Controller
   − AGP v2.0 compliant for 1x and 2x transfer modes
   − Pipelined split-transaction long-burst transfers up to 533 MB/sec
   − Eight level read request queue
   − Four level posted-write request queue
   − Thirty-two level (quadwords) read data FIFO (128 bytes)
   − Sixteen level (quadwords) write data FIFO (64 bytes)
   − Intelligent request reordering for maximum AGP bus utilization
   − Supports Flush/Fence commands
   − Graphics Address Relocation Table (GART)
   − One level TLB structure
   − Sixteen entry fully associative page table
   − LRU replacement scheme
   − Independent GART lookup control for host / AGP / PCI master accesses
   − Windows 95 OSR-2 VXD and integrated Windows 98 / NT5 miniport driver support
• Concurrent PCI Bus Controller
   − PCI bus is synchronous / pseudo-synchronous to host CPU bus
   − 33 MHz operation on the primary PCI bus
   − Supports up to five PCI masters
   − Peer concurrency
   − Concurrent multiple PCI master transactions; i.e., allow PCI masters from both PCI buses active at the same time
   − Zero wait state PCI master and slave burst transfer rate
   − PCI to system memory data streaming up to 132Mbyte/sec
   − PCI master snoop ahead and snoop filtering
   − Six levels (double-words) of CPU to PCI posted write buffers
   − Byte merging in the write buffers to reduce the number of PCI cycles and to create further PCI
      bursting possibilities
   − Enhanced PCI command optimization (MRL, MRM, MWI, etc.)
   − Forty-eight levels (double-words) of post write buffers from PCI masters to DRAM
   − Sixteen levels (double-words) of prefetch buffers from DRAM for access by PCI masters
   − Supports L1/L2 write-back forward to PCI master read to minimize PCI read latency
   − Supports L1/L2 write-back merged with PCI master post-write to minimize DRAM utilization
   − Delay transaction from PCI master reading DRAM
   − Read caching for PCI master reading DRAM
   − Transaction timer for fair arbitration between PCI masters (granularity of two PCI clocks)
   − Symmetric arbitration between Host/PCI bus for optimized system performance
   − Complete steerable PCI interrupts
   − PCI-2.2 compliant, 32 bit 3.3V PCI interface with 5V tolerant inputs
• High-Performance DRAM Controller
   − 64-bit DRAM interface synchronous with host CPU (66//100 MHz) or internal Memory Clock (100 MHz)
   − Concurrent CPU and AGP access
   − Supports both standard PC100 and "Virtual Channel" PC100 SDRAMs as well as FPG and EDO DRAMs
   − Different DRAM types (FPG, EDO, and SDRAM) may be used in mixed combinations
   − Different DRAM timing for each bank
   − Dynamic Clock Enable (CKE) control for SDRAM power reduction
   − Mixed 1M / 2M / 4M / 8M / 16MxN DRAMs
   − 6 banks up to 768MB DRAMs
   − Flexible row and column addresses
   − 64-bit data width only
   − 3.3V DRAM interface
   − Programmable I/O drive capability for MA, command, and MD signals
   − Optional bank-by-bank ECC (single-bit error correction and multi-bit error detection) or EC (error checking
      only) for DRAM integrity
   − Two-bank interleaving for 16Mbit SDRAM support
   − Two-bank and four bank interleaving for 64Mbit SDRAM support
   − Supports maximum 8-bank interleave (i.e., 8 pages open simultaneously); banks are allocated based on LRU
   − Seamless DRAM command scheduling for maximum DRAM bus utilization (e.g., precharge other banks while
      accessing the current bank)
   − Four cache lines (16 quadwords) of CPU/cache to DRAM write buffers
   − Four quadwords of CPU/cache to DRAM read prefetch buffers
   − Concurrent DRAM writeback
   − Read around write capability for non-stalled CPU read
   − Burst read and write operation
   − 5-2-2-2-2-2-2-2 back-to-back accesses for EDO DRAM
   − 6-1-1-1-2-1-1-1 back-to-back accesses for SDRAM
   − BIOS shadow at 16KB increment
   − Decoupled and burst DRAM refresh with staggered RAS timing
   − Programmable refresh rate and refresh on populated banks only
   − CAS before RAS or self refresh
`Sophisticated Power Management Features
   − Independent clock stop controls for CPU / SDRAM, Internal AGP and PCI bus
   − PCI and AGP bus clock run and clock generator control
   − Suspend power plane preserves memory data
   − Suspend-to-DRAM and Self-Refresh operation
   − Dynamic clock gating for internal functional blocks for power reduction during normal operation
   − Low-leakage I/O pads
• General Graphic Capabilities
   − 64-bit Single Cycle 2D/3D Graphics Engine
   − Supports 2 to 8 Mbytes of Frame Buffer located in System Memory
   − Real Time DVD MPEG-2 and AC-3 Playback
   − Video Processor
   − I²C Serial Interface
   − Integrated 24-bit 230MHz True Color DAC
   − Extended Screen Resolutions up to 1600x1200
   − Extended Text Modes 80 or 132 columns by 25/30/43/60 rows
   − DirectX 6 and OpenGL ICD API
• High Performance rCADE3D™ Accelerator
   − 32 entry command queue, 32 entry data queue
   − 4Kbyte texture cache with over 90% hit rates
   − Pipelined Setup/Texturing/Rendering Engines
   − DirectDraw™ acceleration
   − Multiple buffering and page flipping
Setup Engine
   − 32-bit IEEE floating point input data
   − Slope and vertex calculations
   −Back facing triangle culling
   − 1/16 sub-pixel positioning
                    Rendering Engine

   − High performance single pass execution
   − Diffused and specula lighting
   − Gouraud and flat shading
   − Anti-aliasing including edge, scene, and super-sampling
   − OpenGL compliant blending for fog and depth-cueing
   − 16-bit Z-buffer
   − 8/16/32 bit per pixel color formats
                    Texturing Engine
   − D3D compressed texture formats DXT1 and DXT2
   − Anisotropic texture filtering
   − 1/2/4/8-bits per pixel compact palletized textures
   − 16/32-bits per pixel quality non-palletized textures
   − Pallet formats in ARGB 565, 1555, or 444
   − Tri-linear, bi-linear, and point-sampled filtering
   − Mip-mapping with multiple Level-Of-Detail (LOD) calculations and perspective correction
   − Color keying for translucency
                    2D GUI Engine
   − 8/15/16/24/32-bits per pixel color formats
   − 256 Raster Operations (ROPs)
   − Accelerated drawing: BitBLTs, lines, polygons, fills, patterns, clipping, bit masking
   − Panning, scrolling, clipping, color expansion, sprites
   − 32x32 and 64x64 Hardware Cursor
   − DOS graphics and text modes
• DVD
   − Hardware-Assisted MPEG-2 Architecture for DVD with AC-3
   − Simultaneous motion compensation and front-end processing (parsing, decryption and decode)
   − Supports full DVD 1.0, VCD 2.0 and CD-Karaoke
   − Microsoft DirectShow 2.x native support, backward compatible to MCI
   − No additional frame buffer requirements
   − Dynamic frame and field de-interlace filtering for high quality playback on VGA monitors (Bob and Weave)
   − Tamper-proof software CSS implementation
   − Freeze, Fast-Forward, Slow Motion, Reverse
   − Pan-and-Scan support for 16:9 sequence
• Video Processor
   − On-chip Color Space Converter (CSC)
   − Anti-tearing via two frame buffer based capture surfaces
   − Minifier for video stream compression and filtering
   − Horizontal/vertical interpolation with edge recovery
   − Dual frame buffer apertures for independent memory access for graphics and video
   − YUV 4:2:2/4:1:1/4:2:0 and RGB formats
   − Capture / ZV Port to MPEG and video decoder
   − Vertical Blank Interval for Intercast™
   − Overlay differing video and graphic color depths
   − Display two simultaneous video streams from both internal AGP and Capture / ZV Port
   − Two scalers and Color Space Converters (CSC) for independent windows
• Digital Flat Panel (DFP) Interface
   − 85MHz DFP interface supports 1024x768 panels
   − Allows external TMDS transmitter for advanced panel interfaces
• Testability
   − Build-in NAND-tree pin scan test capability
                   

The Apollo VT8501 is a PC Socket-7 system logic North Bridge with integrated 2D / 3D Graphics accelerator. The core logic portion of the chip is based on the popular 100MHz VIA Apollo MVP3 chipset with enhanced features and graphics accelerator based on the Cyber9398DVD from Trident Microsystems, Inc. The combination of the two leading edge technologies provides a stable, cost-effective, and high performance solution for personal computers, imbedded systems, set-top boxes and others. As shown in Figure 1 below, the Apollo MVP4 will interface to:
      • Socket 7 CPU (66 100 MHz)
      • L2 Cache RAM & Tag
      • SDRAM Memory Interface
      • PCI Bus (30 - 33 MHz)
      • Analog RGB Monitor with DDC
      • DFP / Digital Monitor Interface (TMDS)
      • Video Capture / Playback CODECs