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VT73LVP10

Features: 700ps typical propagation delay Differential LVPECL outputs Flow-through pinout -40o C to +85o C operating temperature range 5V - tolerant inputs ESD rating >2000V (Human Body Model) or >200V (Machine Model) Available as die, 8-pin SOIC or 8 pin MSOP packageApplication̶...

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VT73LVP10: Features: 700ps typical propagation delay Differential LVPECL outputs Flow-through pinout -40o C to +85o C operating temperature range 5V - tolerant inputs ESD rating >2000V (Human Body Mo...

VT73LVP10 Data Sheet

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Part Number:
VT73LVP10
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/11/21

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Product Details

Description



Features:

700ps typical propagation delay
Differential LVPECL outputs
Flow-through pinout
-40o C to +85o C operating temperature range
5V - tolerant inputs
ESD rating >2000V (Human Body Model) or >200V (Machine Model)
Available as die, 8-pin SOIC or 8 pin MSOP package


Application

• PECL clock source


Pinout

Connection Diagram


Specifications

Symbol Parameter
Conditions
Min
Typ
Max
Units
VDD Supply voltage
Referenced to GND


6
V
VIN Inputs and Clock Outputs
Referenced to GND
-0.5

6
V
IOUT Soldering Temperature



50
°C
TSTG Storage temperature

-65

150
°C


Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and correct functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.




Description

The Vaishali VT73LVP10 is a general purpose TTL (CMOS) to differential LVPECL translator, with active-LOW enable. The device operates from a single 3.3V supply. When /EN is LOW or open circuit, the device accepts an LVTTL or LVCMOS input and provides differential LVPECL outputs referenced to the positive supply rail. When /EN is HIGH, the Q output is set to the LOW state and QN output is set to the HIGH state.




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