VSC9295

Features: ·Industry Highest Capacity Single Chip TSI - 340 Gbps·25% Less Power Consumption Over Comparable Solutions·Scalable to 1.36 Tbps·Dual Rate 2.5 G / 622 M Standards Based I/OApplication·Core/Metro Networks·Core/Metro Transport·DWDM Switches·Central Switch in 170 Gbps to 340 Gbps STS-1 Groo...

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SeekIC No. : 004543504 Detail

VSC9295: Features: ·Industry Highest Capacity Single Chip TSI - 340 Gbps·25% Less Power Consumption Over Comparable Solutions·Scalable to 1.36 Tbps·Dual Rate 2.5 G / 622 M Standards Based I/OApplication·Core...

floor Price/Ceiling Price

Part Number:
VSC9295
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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268 Transactions

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Upload time: 2024/12/21

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Product Details

Description



Features:

·Industry Highest Capacity Single Chip TSI - 340 Gbps
·25% Less Power Consumption Over Comparable Solutions
·Scalable to 1.36 Tbps
·Dual Rate 2.5 G / 622 M Standards Based I/O



Application

·Core/Metro Networks
·Core/Metro Transport
·DWDM Switches
·Central Switch in 170 Gbps to 340 Gbps STS-1 Grooming Fabric
·Switch Element for 680 Gbps to 1.36 Tbps STS-1 Grooming Fabric
·Bit-slicing Engine for 680 Gbps to 1.36 Tbps STS-1 Grooming Fabric
·Ingress/Egress Device for Multi-terabit STS-1 Grooming Clos Fabric



Specifications

·340 Gbps Aggregate Bandwidth
·Dual Rate TFI-5 Compliant 2.5 Gbps & 622 Mbps High-speed Interfaces
·Dual +2.5V/1.2V Power Supply
·Power Dissipation 19W (typ), 26W (max when VSC9295 is fully utilized) with Power-down for Unused Channels
·45.0 mm 1072 fcBGA Package
·53 MHz 16-bit CPU Interface



Description

The VSC9295 is a 136 x 136 TSI switch IC supporting TFI-5 (STS-48-like frame) data on every input and output. All data
inputs and outputs are differential serial signals running at 2.488 Gbps or 622 Mbps for TDM switching, or 2.488 Gbps,
2.125 Gbps, and 622 Mbps for transparent switching. The device contains a fully nonblocking STS-1 switch matrix surrounded by serial backplane interfaces that incorporate fully integrated clock recovery and synthesis, input equalization, output pre-emphasis, SONET/SDH compliant scrambling,framing, deskewing, and alarms. Ports to drop and insert overhead bytes are included. A multimode CPU interface is used for device configuration and status monitoring.




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