VSC9210

The VSC9210 provides forward error correction for any data rate and protocol operating up to 2.5Gb/s using a block oriented Reed-Solomon Forward Error Correction (FEC) algorithm RS(255,241). The device can be configured as a FEC encoder or a FEC decoder utilizing two 16-bit differential PECL I/O ports to interface with an external high speed multiplexer/ demultiplexer pair. Clock dividers are provided on chip to facilitate control of external PLL circuitry.

For the Encoder, the 1:16 Demultiplexer is used to convert the incoming 2.5Gb/s STS-48 information to a 16 bit parallel data at 155MHz to interface with the VSC9210. After the encoding process, the 16 bit parallel output data from the VSC9210 is obtained at 165MHz and is converted to a 2.65Gb/s data stream using the 16:1 Multiplexer. In the case of the Decoder configuration, the Demultiplexer operates on a 2.65Gb/s data stream while the Multiplexer provides the 2.5Gb/s STS-48 information stream. Clock dividers are incorporated within the VSC9210 to provide control of an external PLL circuit for synthesizing the necessary reference clock for the Multiplexer. In the case of the Bypass mode, the input and output rates are identical and both the Multiplexer and Demultiplexer operate at 2.5Gb/s.