VSC9186

 Bidirectional Quad STS-48/STM-16 or STS-192/ STM-64 Section and Line Termination Device with Pointer Processing and Time Slot Interchange
 Accommodates a +/- 300ppm Difference Between Incoming and Local System Clock and Performs Pointer Processing on Quad Independent STS-48/ STM-16 or a Single STS-192/STM-64
 Pointer Processing of all Concatenation Levels Including STS-192c, STS-48c, STS-12c, STS-3c, and STS-1
 Three ports featuring 16 Serial 622Mb/s Timestream Backplane Interfaces with Integrated CDR to Other Line Interfaces or Switch ICs
 Section/Line OH Drop/Insertion with External Interfaces on All Channels
 Supports Section/Line Overhead Transparency
 Protection Interface Allows Full STS-1/STM-0 Hairpinning and Drop/Continue on Both Tributary and Ring Traffic
 Two Integrated Bidirectional 768 x 288 STS-1 Level Crossconnects
 Embedded Hardware UPSR
 Compliant with SONET and SDH Requirements as Stated in ANSI T1.105, Bellcore GR-253-CORE and ITU-T G.707
 Provides JTAG TAP Controller Conforming to the IEEE 1149.1 Standard
 Bidirectional Path Monitoring

The VSC9186 is a bidirectional quad STS-48/STM-16 or OC-192/STM-64 framer and pointer processor. In addition to full path overhead monitoring, section and line termination are available on line inputs and outputs. A bidirectional protection interface allows both line and tributary traffic to be looped back simultaneously through a companion device. The UPSR is implemented entirely in hardware driven by the STE/LTE logic, pointer interpreter and path overhead monitor.

The VSC9186 can be used in SONET/SDH applications such as Time Slot Interchange (TSI) switches, digital crossconnects, add/drop multiplexers, and DWDM terminal multiplexer applications. The VSC9186 supports TOH transparency off-chip using the XILINX Virtex II (XC2V1000-4FG256C). A verified reference design is available with purchase.