VSC880

Features: • 16x16 Synchronous Serial Crosspoint Switch• Serial Data Rates: 2.0Gb/s• 32Gb/s Aggregate Data Bandwidth• Parallel Switches Can Increase Data Bandwidth in Multiples of 32Gb/s• Designed in Conjunction with the VSC870 Backplane Transceiver• Automatic Wo...

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SeekIC No. : 004543489 Detail

VSC880: Features: • 16x16 Synchronous Serial Crosspoint Switch• Serial Data Rates: 2.0Gb/s• 32Gb/s Aggregate Data Bandwidth• Parallel Switches Can Increase Data Bandwidth in Multiple...

floor Price/Ceiling Price

Part Number:
VSC880
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/12/21

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Product Details

Description



Features:

• 16x16 Synchronous Serial Crosspoint Switch
• Serial Data Rates: 2.0Gb/s
• 32Gb/s Aggregate Data Bandwidth
• Parallel Switches Can Increase Data Bandwidth in Multiples of 32Gb/s
• Designed in Conjunction with the VSC870 Backplane Transceiver
• Automatic Word and Cell Synchronization to the Transceiver
• Two Modes of Operation: Distributed Control Self-routing Packet Mode and Central Control Cell Mode
• Multicast Supported in All Modes
• Supports Variable Length Packets in Packet Mode
• Built-in Flow Control Channel in Packet Mode
• Supports Cell Synchronization in Cell Mode
• Parallel CPU Interface and Parallel Switch Configuration Interface
• Loopback, Built-in Self Test and Scan Functions
• 5V Tolerant TTL Inputs
• Dual 3.3V/2.5V or Dual 3.3V/2.0V Power Supplies
• Serial Port Quadrants Can be Powered Down
• Available in 304 BGA Package



Description

The VSC880 is a 16x16 serial crosspoint switch with serial data rates at 2.125Gb/s. The VSC880 has been designed to operate with the VSC870 backplane transceiver to establish a synchronous high performance switching system with an aggregate bandwidth of 32Gb/s. The switch chip transmits the master word clock (62.5Mb/s), and master cell clock (if used) to all port cards through the serial data channels. The transceivers automatically perform bit alignment, word alignment and cell alignment to the switch chip. The transceiver and switch chip have been optimized for both self-routing and cell-based systems and include special commands for connection requests  selfrouting) and cell synchronous operation (cell based). In addition, a parallel CPU interface can be used to control internal modes and read status information from the switch. A 20-bit interface can also be used to program the  witch matrix in 4 clock cycles. The switch chip runs off of a 3.3V/2.5V or 3.3V/2.0V power supplies. The serial I/O buffers contain on-chip termination resistors (see Application Note 34).




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