VSC8228

·Dual Clock and Data Recovery Architecture for Gigabit Ethernet and Fibre Channel Applications
·FibreTimer^TM Configurable Clock Recovery Unit (CRU): Repeater, Retimer, or Bypassed
·Programmable Input Signal Equalization, Output De-emphasis, and Output Drive Levels
·Analog Signal Detect and Protocol Monitor Indicators
·Optional Half-rate SGMII Clock and Repeated Reference Clock Output
·Built In Self Test Which can Generate and Detect an Unframed 2^7, 2^23, and 2^31 Pseudorandom Bit Stream(PRB ), a User Defined Pattern, and the Fibre Channel CRPAT, CJTPAT, and CSPAT Patterns

The VSC8228 is a dual repeater/retimer for Fibre Channel, Gigabit Ethernet, SONET/SDH, and Infiniband applications. he VSC8228 contains dual FibreTimerTM clock recovery units (CRU) for bidirectional signal conditioning in system terconnect and serial backplane applications. The device supports rates from 125 Mbps up to 4.25 Gbps. Using a single reference cl k for acquisition, the VSC8228 retransmits the incoming serial data synchronously to the reference clock in retimer mo de or to the incoming data in repeater mode. In the retimer mode, add/drop elasticity buffers insert/delete Fibre Chann el fill words to account for timing differences in the incoming data and local reference clock.

An analog signal detect function is integrated into both channels. In the retimer mode, the device monitors the ncoming data for run-length violations and K28.5- symbols. The inputs on both the transmit and receive channels can be looped back to the outputs of the opposite channels for diagnostic purposes. The device provides a built-in pattern generator and checker. An optional half-rate clock for SGMII applications is provided on the receive channel output.

A high degree of signal integrity is maintained via differential I/O, on-chip input and output terminations, input alization, and output de-emphasis. The programmable input equalization circuit compensates for the frequency limitations of long printed circuit board (PCB) traces, backplanes, connectors, and cables. Equalization, de-emphasis, output drive levels, data rate, and other features are configured through industry standard serial interfaces (Two-wire or SPI).

The device may be powered from a single 1.2 V supply, single 1.8 V supply, or both a 1.2 V and 1.8 V supply. The 1.8 V supply is required to meet the LVPECL output swing levels. The device has current-mode logic (CML) inputs and outputs that can be AC-coupled for LVPECL and LVDS compatibility. The IC is packaged in a compact 10mm x 10mm, 64-pin TQFP package. Typical power dissipation for a 1.2 V supply is 360 mW.