VSC8201

The VSC8201 PHY is designed, as per the RGMII version 1.2a specification, to support RGMII operation at a 2.5v I/O supply. In addition to the RGMII requirements specified by the standard, the PHY also has an internal clock delay feature (enabled by setting MII Register 23.8) that adds an internal delay of ~2ns to the RXC and the TXC signals when operating at 2.5v. This feature eliminates the need forPCB trace delays or 2ns buffers in the path of the RXC and TXC traces.

Due to customer interest in using the VSC8201 PHY in RGMII interface mode with a single 3.3v supply, Vitesse has characterized the RGMII I/O timing of the PHY under this condition in the following two configurations:
• Standard RGMII Implementation (i.e. with RXC and TXC trace delays on the PCB)
• RGMII Implementation using the Internal Clock Delay feature.

Since the VSC8201 PHY was not specifically designed for RGMII operation with a 3.3v I/O supply, certain accommodations must be made to the board layout in order to ensure a robust interface. The VSC8201 PHY complies with the I/O timing requirements specified in the RGMII version 1.2a specification. No special board layout considerations other than those mentioned in the standard are required for this implementation.