VSC8184

The VSC8184 combines a clock recovery unit and data retiming with a 1:16 Demultiplexer on a single chip to directly generate 16-bit wide data from an incoming 11.5Gb/s to 12.5Gb/s data stream, for use in SONET STS-192/ SDH STM-64 systems. An on-chip Phase Locked Loop (PLL) with Voltage Controlled Oscillator (VCO) generates a 11.5GHz to 12.5GHz clock, which remains phase locked to the incoming data. The incoming data is retimed and Demultiplexer into 16 parallel outputs. It features a highly flexible reference clock input scheme. The user can select between 180-195MHz or 719-781MHz PECL reference clock inputs. The input serial data sampling point voltage threshold can be adjusted. Additional features include a parity bit (PARITY±) that is clocked out with the 16 parallel data, Bit Order Swap (BITORDER) and Data Polarity Invert (DINVERT). To assist in monitoring device operation a Loss-of-Lock (LOLN) alarm and no reference clock (NOREFN) alarm are provided. The VSC8184 is packaged in a modified 90- ball, Ball Grid Array (BGA).