VSC8132

The VSC8132 demultiplexes a 2.488Gb/s HSPECL serial input datastream (DI+) to 32-bit wide, TTL 77.76Mb/s parallel data outputs D[31:0] for SONET/SDH applications. A 2.488GHz HSPECL input clock (CLKI+) is used to time the incoming data and 3 TTL clock outputs, at frequencies of 77.76MHz, 51.84MHz, and 38.88MHz, are generated for upstream devices (DATACLK78, CLK51, CLK38). Odd or even parity is performed on the incoming high-speed data via the TTL Parity Select input (PARSEL), and a TTL Parity output (PARITY) is provided to indicate parity of the input data. Frame Detect on the incoming data is controlled via the Frame Detect Inhibit (OOFN) and Reset (RESET) TTL inputs. A frame detect monitors the incoming data steam and screens for 2 bits in A1 byte out of the 8 bits and 2 bits of A2 byte out of the 8 bits. When a Frame Detect occurs, a synchronization TTL output (SYNC) will be set. Alarm indicators are used to monitor the activity of the clock and data with TTL compatible control inputs (ALMRESET) and outputs (DTALARM, CKALARM).

Only a single 3.3V power supply is required for device operation. The VSC8132 is packaged in a thermally- enhanced 128-pin, 14x20x2mm PQFP package.