VSC8131

• 2.488Gb/s 32:1 Mux with Clock Generator
• SONET STS-48/SDH STM-16
• LVPECL Differential High Speed Serial Data and Clock Outputs
• 32 TTL Parallel Data Inputs with Odd/Even Parity Check
• 128 Pin, 14x20x2 mm Enhanced-PQFP
• Single 3.3V Supply
• 2.15W Max Power Dissipation

The VSC8131 multiplexes 32 TTL compatible 77.76Mb/s Parallel Data Inputs (D0-D31) into a single LVPECL 2.488 Gb/s serial output (DO+) for use in SONET STS-48/SDH STM-16 systems. An integrated Clock Multiplier Unit (CMU) generates a LVPECL 2.488 GHz clock signal (CO+) from an externally supplied LVPECL compliant 77.76MHz reference clock (REFCLK+) which is used to retime the transmitted serialized data. A Divide-by-32 TTL clock output (CK78OUT) is used as a clock input (CK78IN) for timing of the parallel data inputs. Parity Checking (PARBIT) is performed on the incoming data with a selectable even or odd TTL parity mode input (PARMODE) and a TTL Parity Error (PARERR) output. A TTL Loss Of Lock (LOL) output indicator is used to report the loss of the REFCLK+ or for conditions resulting in the CMU losing lock to incoming clock.