VSC8121

The VSC8121 is a monolithic Phase Locked Loop (PLL) based clock generator designed for telecommunications systems operating at 2.5Gb/s. The VSC8121 incorporates a reactance-based (LC) Voltage Controlled Oscillator (VCO) with low phase noise. The PLL's loop filter is on-chip.

The VSC8121 has a differential 2.488GHz CML clock output (CO/CON) signal, a single-ended TTL lowspeed clock (LSCLK) output equivalent in frequency to that of the reference clock, and a TTL reference clock input selectable for 51.84MHz, 77.76MHz or 155.52MHz. TTL inputs REFSEL[0:1] are used to make this selection.

A clean REFCLK signal is required since jitter below the PLL loop bandwidth, which is present on the REFCLK input, will appear on the output. Jitter on REFCLK at frequencies above the loop bandwidth will be attenuated by the PLL. The state of REFSEL[0:1] will select which frequency is expected on the REFCLK input.