VSC7203

The VSC7203 has the following features including 2-port Switch Capable of Passing SCI Packets;Multiplezers Allow Bypassing Around any Port for Faulty Node Isolation;Sends and Receives SCI Symbols Every 2 ns for 1 GB/s Data Rate Per Port;One Port Conforms to Low Voltage DifferentialSignalling (LVDS) Standard (IEEE Std. 1596.3);+3.3V and +2V Power Supplies;301 BGA Package (50 mil spacing, 27mm/side);IFRF Std 1149.1 Test Access Port for Diagnostics and Boundary Scan.

This Node Bypass circuit is intended to serve the purpose of isolation of SCI nodes. Multiple copies of this circuit would be interposed in a SCI ringlet, as required , and in normal operation pass SCI  packets from one node to another while introducing minimum latency.A faulty node can be electronically bypassed by assertion of the proper control signals. The LVD input and output busses are intended to connect SCI nodes controlled by VSC7201A "Data pump"  circuits.Tne outher input ana output busses use level-shifted ECL signaling (VECL) and are intended to connect to other VSC7203 Node Bypass circuits.The node bypass circuit uses the input strobe for each input port as the source for the clock driving the two register pipeline to the selected output port. An internal 1 GHz PLL regenerates the selected input clock phase so that an unlimited number of circuits can be interconnected.The node bypass circuit is a switch that has two basic modes of operation: NORMAL and BYPASS mode.In NORMAL mode, SCI packets are transmitted from the SCI node to a node bypass circuit and from a node bypass circuit to the SCI node. In BYPASS mode, SCI packets are transmitted fmm node bypass circuit to node bypass circuit. While in BYPASS mode, SCI packets may be sent to an 5CI node, to the node bypass circuit,and back to the same SCI node for diagnostic checking without interfering with ringlet operation.

During SAMPLF/PRELOAD,inputs are registered into the boundary scan shift register in the Capture-DR state. When the ORCAPT bit is high (enabled), the outputs a} registered into the boundary scan shift register as well. Otherwise, the boundary scan shift register does not load the output values when ORCAPT is low. Data is shifted in the boundary scan shift register in the Shift-DR state. The boundary scan output registers are parallel loaded and the outputs of the VSC7203 are driven on the rising edge of TCK on the Update-DR state.