VSC1500TC

The VSC1500TC is a test chip personalizalion of the VSC1500 high speed GaAs Gate Array. This chip is packaged in a ceramic 52 pin leadless chip carrier for use in the VSC1500DUT evaluation board. Test structures utilizing high speed I/O,high speed cells,translator cells, low power cells, ECL I/O, and combinations of these have been included. The user can test speed, temperature sensitivity, power supply sensitivity, and I/O loading sensitivity by measuring these structures. Ail macros referred to are fully described in the VSC1500 Design Manual. The following is a description of the test structures found in the VSC1500TC. This is the output from a chain of 65 low power inverters without additional loading. This structure is designed to establish the intrinsic delay characteristics of the low power 2-input NOR macro. The delay per gate derived from the measurement of this test structure should agree with the results from the ring oscillator.Inverter chain i is physically near the VEE sources on the chip and in combination with Inverter Chain 6 can be used to asses the effects of backgating by comparing the performance with or without VEE connected.

This is the output of a chain of 65 low power inverters with every other inverter loaded with a fanout of 3. This structure in conjunction with Inverter Chaln 4 can be used to asses the effect of fanout on rising and falling edges independently.All the inverter chains are driven by the same external signal. The outputs are buffered by an ECL 100K output buffer. Another path, also buffered with an ECL 100K output buffer, is available that bypasses the inverter chains so that a true representation of inverter chain delays can be measured.This structure is a differential ECL input buffer. The true and complement outputs are brought out through independent ECL output buffers. This structure can be used to evaluate the DC and AC characteristics of the VSC1500 ECL UO buffers.

This structure connects a differential high speed input directly into a differential high speed output. This structure is useful in evaluating the bandwidth characteristics of the high speed I/O section of the chip.This is a 23 stage ring oscillator made up of 24 SCFL inverters. The output is brought off via a T1 cell and an ECL 100K output macro.