VSB 1400

The VSB 1400 has the following features including Drives 48mA VSB bus signals: BREQ*, DS*, BUSY*,PAS*;Input hysteresls allows device to monitor VSB signals without additional input buffers;Available in Commercial, Industrial and Military temperature ranges;Bus interface circuitry for multi-master VSB systems.

The VSB 1400 is a CMOS device which incorporates the protocol logic, drivers and buffers required to interface a master,typically a CPU, to the VSB(VME Subsystem Bus). It is packaged in compact 24 pin, 300 mil wide DIP or 28 pin LCC.The VSB 1400 contains a VSB bus requester, controller and arbiter.Therequesterportionofthedevice asserts aVSBbus request in response to a request from the local master. The controller portion of the VSB 1400 supervises all the handshaking between the local master and the slaves. The VSB 1400 is designed to function in a multi-master VSB system, and can reside in any slot. The protocols in the VSB 1400 are fully asynchronous.This device is designed to function with any type of slave device or circuitry which meets the VSB specifications.If the VSB 1400 does not match the requirements of the design, a programmable version is available (the PLX 448) which allows the user to customize all inputs, outputs and logic. Programming is performed using industry standard tools such as ABEL'" or CUPL"' software and commonly available PLD programming hardware. Contact PLX for a data sheet on the PLX 448 and other information.

The VSB 1400 will deassert DS* when data has been transferred to or from the responding and participating slaves. To deassert DS*, the VSB 1400 must receive WAIT* high from all the slaves, indicating that they have completed thatparticular data transfer operation. For the last data cycle (or the only data cycle in the case of a single transfer cycle) the responding slave must drive AC low before driving ACK* low.The VSB 1400 will drive ADDEN* (the address buffer enable signal) provided thatAC is deasserted and DS* is high. These two conditions indicate that the previous data cycle is complete. The local master is now ready to put the address on the bus.