Features: Fully integrated H.261 video de-multiplexer Inputs an H.261 bitstream. Outputs error corrected run length coded coefficients. Interfaces directly to the VP2615 H.261 decoder Extracts side information and status for transfer to a System Controller User definable system level options for ...
VP2614: Features: Fully integrated H.261 video de-multiplexer Inputs an H.261 bitstream. Outputs error corrected run length coded coefficients. Interfaces directly to the VP2615 H.261 decoder Extracts side...
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Supply voltage VDD Input voltage VIN Output voltage VOUT Clamp diode current per pin IK (see note 2) Static discharge voltage (HBM) Storage temperature TS Ambient temperature with power applied TAMB Junction temperature Package power dissipation |
-0.5V to 7.0V -0.5V to VDD + 0.5V -0.5V to VDD + 0.5V 18mA 500V -55°C to 150°C 0°C to 70°C 100°C 1000mW |
The VP2614 Video De-Multiplexer forms part of the Mitel Semiconductor chip set for video conferencing, video telephony, and multimedia applications. It extracts video parameters and run length coded DCT coefficients from an H.261 bitstream. Elements of the data which have been variable length coded according to the specification are decoded within the device. It produces tagged data, aligned to a macroblock timing structure, in the format needed by the VP2615 Decoder. Side information and status bits are separately made available for the system controller.
The VP2614 will accept data up to a peak rate of 4 Mbits per second, but with an average rate up to 2 Mbits per second. The bursty nature of the input, together with the fact that each coded picture does not use the same number of bits, requires the provision of a received data buffer. Since the VP2615 Decoder accepts macroblock data as it becomes available, it is not necessary to provide storage for a complete coded picture. Worst case analysis has shown that a buffer size of 256K bits is adequate in practice for bit rates up to 2Mb/sec.
The incoming sequence is coded with a strict syntax, and the VP2614 must identify and align with this sequence before correct decoding is possible. Storage for this alignment is contained within the external buffer. The device monitors that lock is always valid, and reports to the system controller. Error correction bits are ignored.