Features: SpecificationsDescriptionThe VL82C164 has the following features including Provides simultaneous hardwareassist for bit-mapped graphics operations on four independent memory planes. VL82C164includes two 32-bit barrel shifters in each Raster Op section;Performance increase over software i...
VL82C164: Features: SpecificationsDescriptionThe VL82C164 has the following features including Provides simultaneous hardwareassist for bit-mapped graphics operations on four independent memory planes. VL82C1...
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The VL82C164 has the following features including Provides simultaneous hardwareassist for bit-mapped graphics operations on four independent memory planes. VL82C164 includes two 32-bit barrel shifters in each Raster Op section;Performance increase over software implementations: 4 x (Planes) x Software;Supports any type of raster image manipulation, including CRT displays and laser printers;Implements 256 possible raster operations on source, destination,and pattern data;100-lead plastic quad flat pack (PJQFP) package; 5 V supply;Low power CMOS technology.
The VL82C164 Quad Raster Op ALU(0R0) provides hardware-assisted performance enhancement for bit manipulation operations in bit-mapped graphics displays. These operations, called bit block translation (BITBLT), allow bit-mapped images to be combined and manipulated by logical operations.These operations include AND, OR, and XOR, as well as a wide range of others which can be arbitrarily defined by the user. The QRO also contains Mask Registers which provide automatic clipping capability at the boundaries of the image section being manipulated.The BITBLT operation is applicable to a wide variety of graphics operations,including proportionally spaced text display using arbitrary fonts, attributes,and enhancements. Successive applications of BITBLT can perform such operations as scaling, filling, and texturing.
In a typical application, the ORO VL82C164 operates on display data in 16-bit words that are latched into input buffers by external hardware. Source, Destination,Pattern, and Output Registers have dedicated strobe signals, which eliminate the delays associated with address decode. Each of the four independent Raster Op sections has a dedicated chip select to allow maximum speed as well as allowing the same data to be loaded into multiple sections simultaneously. Each section can also be selected via a pair of address lines,allowing a linear address map for host access. For each cycle of operation,the Source and Destination Registers are loaded and the source is aligned according to a previously loaded shift count and combined with the destination and pattern data. The result is written back to the display memory via the dedicated strobe. The QRO can scan forward or backward through the display memory. For cases where only part of the memory word is to be modified, the QRO automatically applies the appropriate mask at each end of the scan.