VCH16240

Features:

1.65V to 3.6V VCC supply operation
3.6V tolerant control inputs and outputs
Bushold on data inputs eliminates the need for external pull-up/pull-down resistors
t PD
 3.9 ns max for 3.0V to 3.6V VCC
 5.3 ns max for 2.3V to 2.7V V  CC
 6.0 ns max for 1.65V to 1.95V V CC
Uses patented noise/EMI reduction circuitry
Latch-up conforms to JEDEC JED78
ESD performance:
  Human body model > 2000V
  Machine model > 200V


Pinout




Specifications

Supply Voltage (V _CC)........................... -0.5V to + 4.6V
DC Input Voltage (V_I)...............................- 0.5V to 4.6V
Output Voltage (V_O  ) (Note 2)....-  0.5V to V_CC  + 0.5V
DC Input Diode Current (I_IK )
V _I   <0V.......................................................... - 50 mA
DC Output Diode Current (I_OK )
V _O  < 0V..........................................................- 50 mA
DC Output Source/Sink Current
(I_OH /I_OL ).......................................................± 50 mA
 DC V_CC or GND Current per
Supply Pin (I_CC   or GND) ..............................±100 mA
Storage Temperature Range (T ) ....-65°C to +150°C


Description

The ALVCH16240 contains sixteen inverting buffers with 3-STATE outputs to be employed as a memory and address driver, clock driver, or bus oriented transmitter receiver. The device is nibble (4-bit) controlled. Each nibble has separate 3-STATE control inputs which can be shorted together for full 16-bit operation. 

The ALVCH16240 data inputs include active bushold cir- cuitry, eliminating the need for external pull-up resistors to hold unused or floating inputs at a valid logic level. The 74ALVCH16240 is designed for low voltage (1.65V to 3.6V) V  applications with output capability up to 3.6V. CC The 74ALVCH16240 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining low CMOS power dissipation.