Features: JEDEC 200 Pin DDR Unbuffered Small-Outline,Dual In-Line memory module (SODIMM);33,554,432 x 64 bit organization. Utilizes High Performance 16M x 16 DDR SDRAM in TSOPII-66 Packages Single +2.5V (± 0.2V) Power Supply Programmable CAS Latency, Burst Length, and Wrap Sequence (Sequential &a...
V826632B24S: Features: JEDEC 200 Pin DDR Unbuffered Small-Outline,Dual In-Line memory module (SODIMM);33,554,432 x 64 bit organization. Utilizes High Performance 16M x 16 DDR SDRAM in TSOPII-66 Packages Single ...
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Features: JEDEC 200 Pin DDR Unbuffered Small-Outline,Dual In-Line memory module (SODIMM);16,777,2...
Features: JEDEC 200 Pin DDR Unbuffered Small-Outline,Dual In-Line memory module (SODIMM);16,777,2...
Features: 184 Pin Unbuffered 16,777,216 x 64 bit Organization DDR SDRAM Modules Utilizes High Per...
JEDEC 200 Pin DDR Unbuffered Small-Outline,Dual In-Line memory module (SODIMM);33,554,432 x 64 bit organization.
Utilizes High Performance 16M x 16 DDR SDRAM in TSOPII-66 Packages
Single +2.5V (± 0.2V) Power Supply
Programmable CAS Latency, Burst Length, and Wrap Sequence (Sequential & Interleave)
Auto Refresh (CBR) and Self Refresh
All Inputs, Outputs are SSTL-2 Compatible
8192 Refresh Cycles every 64 ms
Serial Presence Detect (SPD)
DDR SDRAM Performance
Parameter | Symbol | Rating | Unit |
Ambient Temperature | TA | 0 ~ 70 | |
Storage Temperature | TSTG | -55 ~ 125 | |
Voltage on Any Pin relative to VSS | VIN, VOUT | -0.5 ~ 3.6 | V |
Voltage on VDD relative to VSS | VDD | -0.5 ~ 3.6 | V |
Voltage on VDDQ relative to VSS | VDDQ | -0.5 ~ 3.6 | V |
Output Short Circuit Current | IOS | 50 | mA |
Power Dissipation | PD | 8 | W |
Soldering Temperature • Time | TSOLDER | 260 • 10 | • Sec |
Note: Operation at above absolute maximum rating can adversely affect device reliability
The V826632B24S memory module is organized 33,554,432 x 64 bits in a 200 pin memory module.The 32M x 64 memory module uses 8 Mosel-Vitelic 16M x 16 DDR SDRAM. The x64 modules are ideal for use in high performance computer systems where increased memory density and fast access times are required.