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V54C365404VD(L)

Features: 4 banks x 4Mbit x 4 organizationHigh speed data transfer rates up to 143 MHzFull Synchronous Dynamic RAM, with all signals referenced to clock rising edgeSingle PulsedRAS InterfaceData Mask for Read/Write ControlFour Banks controlled by BA0 & BA1ProgrammableCAS Latency: 2, 3Programma...

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SeekIC No. : 004539965 Detail

V54C365404VD(L): Features: 4 banks x 4Mbit x 4 organizationHigh speed data transfer rates up to 143 MHzFull Synchronous Dynamic RAM, with all signals referenced to clock rising edgeSingle PulsedRAS InterfaceData Mas...

V54C365404VD(L) Data Sheet

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Part Number:
V54C365404VD(L)
Supply Ability:
5000

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  • 1~5000
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  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/12/21

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Product Details

Description



Features:

 4 banks x 4Mbit x 4 organization
 High speed data transfer rates up to 143 MHz
 Full Synchronous Dynamic RAM, with all signals referenced to clock rising edge
 Single Pulsed RAS Interface
 Data Mask for Read/Write Control
 Four Banks controlled by BA0 & BA1
 Programmable CAS Latency: 2, 3
 Programmable Wrap Sequence: Sequential or Interleave
 Programmable Burst Length:
   1, 2, 4, 8 and full page for Sequential Type
   1, 2, 4, 8 for Interleave Type
 Multiple Burst Read with Single Write Operation
 Automatic and Controlled Precharge Command
 Random Column Address every CLK (1-N Rule)
 Suspend Mode and Power Down Mode
 Auto Refresh and Self Refresh
 Refresh Interval: 4096 cycles/64 ms
 Available in 54 Pin 400 mil TSOP-II
 LVTTL Interface
 Single +3.3 V ±0.3 V Power Supply


Pinout

Connection Diagram


Specifications

Operating temperature range......................................................0 to 70°C
Storage temperature range ...................................................-55 to 150°C
Input/output voltage.................................................... -0.3 to (VCC+0.3) V
Power supply voltage ............................................................. -0.3 to 4.6 V
Power dissipation ..................................................................................1 W
Data out current (short circuit)...........................................................50 mA


Description

The V54C365404VD(L) is a four bank Synchronous DRAM organized as 4 banks x 4Mbit x 4. The V54C365404VD(L) achieves high speed data transfer rates up to 143 MHz by employing a chip architecture that prefetches multiple bits and then synchronizes the output data to a system clock

All of the control, address, data input and output circuits are synchronized with the positive edge of an externally supplied clock.

Operating the four memory banks in an interleaved fashion allows random access operation to occur at higher rate than is possible with standard DRAMs. A sequential and gapless data rate of up to 143 MHz is possible depending on burst length, CAS latency and speed grade of the V54C365404VD(L).




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