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V54C333322V

Features: JEDEC Standard 3.3V Power Supply The V54C333322V is ideally suited for high performance graphics peripheral applications Single Pulsed RAS Interface Programmable CAS Latency: 2, 3 All Inputs are sampled at the positive going edge of clock Programmable Wrap Sequence: Sequential or Interle...

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SeekIC No. : 004539961 Detail

V54C333322V: Features: JEDEC Standard 3.3V Power Supply The V54C333322V is ideally suited for high performance graphics peripheral applications Single Pulsed RAS Interface Programmable CAS Latency: 2, 3 All Inpu...

V54C333322V Data Sheet

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Part Number:
V54C333322V
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

 JEDEC Standard 3.3V Power Supply 
The V54C333322V is ideally suited for high performance graphics peripheral applications 
Single Pulsed RAS Interface 
Programmable CAS Latency: 2, 3 
All Inputs are sampled at the positive going edge of clock 
Programmable Wrap Sequence: Sequential or Interleave 
Programmable Burst Length: 1, 2, 4, 8 and Full Page for Sequential and 1, 2, 4, 8 for Interleave 
DQM 0-3 for Byte Masking 
Auto & Self Refresh 
2K Refresh Cycles/32 ms 
Burst Read with Single Write Operation


Pinout

Connection Diagram


Specifications

Operating temperature range ...........................................0 to 70°C
Storage temperature range .........................................-55 to 150°C
Input/output voltage.......................................... -0.3 to (VCC+0.3) V
Power supply voltage ................................................... -0.3 to 4.6 V
Power dissipation ....................................................................... 1 W
Data out current (short circuit)................................................. 50 mA


Description

The V54C333322V is a 33,554,432 bits synchronous high data rate DRAM organized as 2 x 524,288 words by 32 bits. The device is designed to comply with JEDEC standards set for synchronous DRAM products, both electrically and mechanically. Synchronous design allows precise cycle control with the system clock. The CAS latency, burst length and burst sequence must be programmed into device prior to access operation.




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