Features: • Power supply 3.3 V
• Multistandard differential signal electrical interface
• 12 electrical data channels
• Asynchronous, AC-coupled optical link
• 12 optical data channels
• Transmission data rate of up to 1600 Mbit/s per
channel, total link data rate up to 19 Gbit/s
• 850 nm VCSEL array technology
• PIN diode array technology
• 62.5 µm graded index multimode fiber ribbon
• MT based optical port
• SMD technology
• IEC Class 1M laser safety compliant
• GBE mask compliant modules availableApplicationTelecommunication
• Switching equipment
• Access network Data Communication
• Interframe (rack-to-rack)
• Intraframe (board-to-board)
• On board (optical backplane)Specifications
|
Parameter |
Symbol |
Limit Values |
Unit |
|
min. |
max. |
|
Supply Voltage |
VCCVEE |
0.3 |
4.5 |
V |
|
Data/Control Input Levels1) |
V1N |
0.5 |
VCC+0.5 |
V |
|
Data Input Differential Voltage2) |
|VlD| |
|
2.0 |
V |
|
Operating Case Temperature3) |
TCASE |
0 |
80 |
°C |
|
Storage Ambient Temperature |
TSTG |
20 |
100 |
°C |
|
Operating Moisture |
|
20 |
85 |
% |
|
Storage Moisture |
|
20 |
85 |
% |
|
ESD Resistance
(all pins to VEE, human body model)4)
|
|
|
1 |
kV |
DescriptionV23815-U1306-M136 is a parallel optical link for high-speed data transmission. A complete PAROLI system consists of a transmitter module, a 12-channel fiber optic cable, and a receiver module. The transmitter supports LVDS, CML and LVPECL differential signals. The receiver module is described for the LVDS electrical output only. A specification for Infineon's adjustable CML output can be provided separately.
The V23815-U1306-M136 receiver module converts parallel optical input signals into parallel electrical output signals. The optical signals received are converted into voltage signals by PIN diodes, transimpedance amplifiers, and gain amplifiers. There are two different modules available for LVDS and Infineon's adjustable CML output. This description only refers to a module with LVDS output. A module description for CML output can be provided separately.
The data rate of V23815-U1306-M136 is up to 1600 Mbit/s for each channel. The receiver module's min. data rate of 500 Mbit/s is specified for the CID1) worst case pattern (disparity 72) or any pattern with a lower disparity.
Additional Signal Detect outputs (SD1 active high / SD12 active low) show whether an optical AC input signal is present at data input 1 and/or 12. The signal detect circuit can be disabled with a logic low at ENSD. The disabled signal detect circuit will permanently generate an active level at Signal Detect outputs, even if there is insufficient signal input. This could be used for test purposes.A logic low at LVDS Output Enable (OEN) sets all data outputs to logic low. SD outputs will not be effected. All non data signals of V23815-U1306-M136 have LVCMOS levels. Transmission delay of the PAROLI system is at a maximum 1 ns for the transmitter, 1 ns for the receiver and approximately 5 ns per meter for the fiber optic cable.
V23815-U1306-M136 Data Sheet
