V23815-U1306-M130

The V23815-U1306-M130 receiver module converts parallel optical input signals into parallel electrical output signals. The optical signals of V23815-U1306-M130 received are converted into voltage signals by PIN diodes, transimpedance amplifiers, and gain amplifiers. All output data signals are Low Voltage Differential Signals (LVDS). The data rate is 250-1600 Mbit/s for each channel. Optical input data should be DC balanced within 144 bits. The maximum time interval of consecutive 0's and 1's (run length) should not exceed 72 bits. This will ensure that the output jitter values given for the transmitter and receiver in this data sheet will be met. Otherwise, jitter values might be exceeded. Additional Signal Detect outputs (SD1 active high / SD12 active low) show whether an optical AC input signal is present at data input 1 and/or 12. The signal detect circuit can be disabled with a logic low at ENSD. The disabled signal detect circuit will permanently generate an active level at Signal Detect outputs, even if there is insufficient signal input. This could be used for test purposes.

A logic low at LVDS Output Enable sets all data outputs to logic low. SD outputs will not be effected. All nondata signals of V23815-U1306-M130 have LVCMOS levels. Transmission delay of the PAROLI system is at a maximum 1 µs for the transmitter, 1 µs for the receiver and approximately 5 ns per meter for the fiber optic cable.