Up to 60,000

The pASIC 3 family of devices Up to 60,000 have a range of 4,000 to 60,000 usable PLD gates. pASIC 3 FPGAs are  fabricated on a 0.35 µm four-layer metal process using QuickLogic's" patented ViaLink" technology to provide a unique combination of high performance, high density, low cost, and extreme ease-of-use.

The pASIC 3 family of devices Up to 60,000 contain a range of 96 to 1,584 logic cells (see Table 1). With a range of 74 to 316 I/Os, the pASIC 3 family is available in many device/package combinations (see Table 2).

Software support for the complete pASIC 3 family Up to 60,000 is available through two basic packages. The turnkey QuickWork package provides the most complete FPGA software solution from design entry to logic synthesis, to place and route, to simulation. The QuickToolsTM for Workstations package provides a solution for designers who use Cadence, ExemplarTM, Mentor, Synopsys, Synplicity, ViewlogicTM, AldecTM, or other third-party tools for design entry, synthesis, or simulation.