UTXQ512-AN-000

This application note describes how to use two UT9Q512 4M SRAMs and one UT54ACS151 logic device to mimic a 1Mx1 SRAM. As shown below, the single bit is written into three locations of the same. When the data is read out, UTXQ512-AN-000 is used in a voting system to select either a 0 or a 1 output. This voting method virtually makes it immune to SEU hits. Since the bits of a word are not physically adjacent on the die, it is nearly impossible for one particle to cause two bits to flip in the same word. As such, it would require multiple particle hits to cause an upset.

The system timing of UTXQ512-AN-000 results in maximum read cycle of 48ns, (25ns SRAM read + 23ns input to Y). For better system performance Aeroflex UTMC can screen for memories with read cycles access times down to 17 ns.

The timing analysis above assumes capacitive output loads of 50 pF or less. If the system loading is greater than 50 pF, the user should consult the "Operational Frequency vs. Load Capacitance" application note to calculate the true performance of the design.

If a tri-statable output is required, then additional logic would be required. Aeroflex UTMC has the following logic devices with tristate controlled outputs: UT54ACS244, UT54ACS245, UT54ACS365, UT54ACS373, UT54ACS374, and UT54ACS541. Each of these devices has a non-inverting tri-statable output.

If the 4M SRAMs are packaged in our shielded package, they can withstand a total dose of 100K rads(Si) in most orbits. The UTXQ512-AN-000 can be purchased with a total dose hardness ranging from 100K rads(Si) to 1 Mrad.

This design example requires more board real estate and a new board layout, along with the additional timing analysis, mentioned above, to replace the obsoleted BAE Systems 1M x 1 SRAM parts. The parts shown would use approximately 1.75 square inches of board space.